我想单独设置 std_logic_vector 的位,以便为单个位或一组位轻松设置注释。这是我所拥有的:
signal DataOut : std_logic_vector(7 downto 0);
...
DataOut <= ( 5=>'1', -- Instruction defined
4=>'1', -- Data length control bit, high=8bit bus mode selected
3=>'1', -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display
2=>'0', -- Double height font type control byte, not selected
1 downto 0=>"01", -- Select Instruction table1
others=>'0' -- for bits 6,7
);
但是,我对“downto”语句有疑问,使用 Xilinx ISE 时出现以下错误:
Type std_ulogic does not match with a string litteral
避免使用等效的任何解决方案
1=>'0',
0=>'1',
并允许我逐块设置位?