在以下代码BCDtoSevenDecode中，采用 4 位输入并将其解码以用于七段显示。解码结果存储在resultx变量中。然后将所有 resultx 变量传递给 4x1 Mux。我正在使用 xilinx 来编译这个 verilog 代码。代码编译并带有警告：
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <select> is never assigned.
我无法找出问题所在，所以我在这里咨询专家。
这是代码：
module Counter(input clk, input reset, output[3:0]SsdEnable, output [6:0]DecodedOut, output reg [3:0]temp1, output reg [3:0]temp2 , output reg [3:0]temp3, output reg [3:0]temp4);
wire [6:0] Result1,Result2,Result3,Result4;
reg [3:0] count1,count2,count3,count4;
wire [25:0]loop;
wire [11:0]counter;
reg [1:0]Sel;
SevenDecoder u1(count1,Result1);
SevenDecoder u2(count2,Result2);
SevenDecoder u3(count3,Result3);
SevenDecoder u4(count4,Result4);
Mux u5(Result1,Result2,Result3,Result4,Sel,DecodedOut );
Decoder_2x4 u6(Sel,SsdEnable);
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
count1<=0;
count2<=0;
count3<=0;
count4<=0;
//counter=0;
end
else
begin
if(loop==49999999)
begin
count1<=count1+1;
if(count1==10)
begin
count1<=0;
count2<=count2+1;
end
if(count2==10)
begin
count2<=0;
count3<=count3+1;
end
if(count3==10)
begin
count3<=0;
count4<=count4+1;
end
if(count4==10)
begin
count1<=0;
count2<=0;
count3<=0;
count4<=0;
end
temp1<=count1;
temp2<=count2;
temp3<=count3;
temp4<=count4;
end
loop=loop+1;
end
end
always @(posedge clk or negedge reset)
begin
if(!reset)
Sel=0;
else
begin
if(counter==1000)
begin
Sel=0;
end
end
counter=counter+1;
end
endmodule
module SevenDecoder(input [3:0]i , output[6:0] out);
assign out[0]= (i == 0 || i == 2 || i == 3 || i == 5 || i == 6 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[1] = (i == 0 || i == 1 || i == 2 || i == 3 || i == 4 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[2] = (i == 0 || i == 1 || i == 3 || i == 4 || i == 5 || i == 6 || i == 7 || i == 8 || i == 9) ? 0 : 1;
assign out[3]= (i == 0 || i == 2 || i == 3 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
assign out[4]= (i == 0 || i == 2 || i == 6 || i == 8) ? 0 : 1;
assign out[5]= (i == 0 || i == 4 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
assign out[6]= (i == 2 || i == 3 || i == 4 || i == 5 || i == 6 || i == 8 || i == 9) ? 0 : 1;
endmodule
module Mux(input [6:0]in1,input [6:0]in2,input [6:0]in3,input [6:0]in4, input [1:0]sel, output [6:0]out);
assign out=(sel==0)?in1:
(sel==1)?in2:
(sel==2)?in3:
(sel==3)?in4:0;
endmodule
module Decoder_2x4(input [1:0]sel, output [3:0]selSSD);
assign selSSD=(sel==0)? 4'b1110 :
(sel==1)? 4'b1101 :
(sel==2)? 4'b1011 :
(sel==3)? 4'b0111 :0;
endmodule
是什么导致了这个问题？
编辑：
我已经在这里发布了整个代码。我一直在尝试调试它，但我未能在此代码中找到错误。
此代码不提供任何输出。它应该显示变化的值，cnt1,cnt2,cnt3,cnt4以证明值正在增加，但事实并非如此。