我想实现用于 256 位向量的汉明权重计算的 K&R 算法。我在 vhdl 中编写了我的代码:
entity counter_loop is
Port ( dataIn : in STD_LOGIC_VECTOR (255 downto 0);
dataOut : out STD_LOGIC_VECTOR (8 downto 0);
threshold : in STD_LOGIC_VECTOR (8 downto 0);
clk : in STD_LOGIC;
flag : out STD_LOGIC);
end counter_loop;
architecture Behavioral of counter_loop is
signal val : STD_LOGIC_VECTOR (255 downto 0) := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
begin
process (clk)
variable count : STD_LOGIC_VECTOR (8 downto 0):= "000000000";
begin
flag <= '0';
val <= dataIn;
--if(clk'event and clk = '1') then
while (val > 0) loop
count := count+1;
val <= (val and (val-1));
if (count > threshold) then
flag <= '1';
end if;
end loop;
dataOut <= count;
--end if;
end process;
end Behavioral;
但是,在使用 Xilinx 合成它时,错误出现为
第 53 行:超出非静态循环限制
请问有什么线索吗?
PS:第 53 行是 - while (val > 0) 循环