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我尝试在 FPGA LED 上为 KITT 扫描仪编写 VHDL 代码,但我需要更改此代码:

  with state select 
            led1 <= '1' when forward1,
                '0' when others;

    with state select
        led2 <= '1' when forward2,
            '0' when others;

    with state select
        led3 <= '1' when forward3, 
            '0' when others;

    with state select
        led4 <= '1' when forward4,
            '0' when others;

   with state select 
                    led1,led2,led3 <= '1' when forward1,
                        '0' when others;
      with state select
                   led2, led3,led4 <= '1' when forward2,
                    '0' when others;
with state select
                   led3, led4,led5 <= '1' when forward2,
                    '0' when others;

但是当我这样做时,我收到错误 - 预期的“(”或另一个。如何更改此代码以更改乘法输出?

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1 回答 1

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你可以这样做:

led_select : process(state)
begin
  case state is
    when forward1 =>
     led_states <= "00111";
    when forward2 =>
     led_states <= "01110";
    when forward3 =>
     led_states <= "11100";
    when others =>
     led_states <= (others => '0');
  end case;
end process;

led1 <= led_states(0);
led2 <= led_states(1);
led3 <= led_states(2);
led4 <= led_states(3);
led5 <= led_states(4);

led_states声明为的信号在哪里signal led_states : std_logic_vector(4 downto 0);

于 2012-10-31T11:25:05.713 回答