1

首先是这个简单的加法器实体：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

entity adder is
    Port ( a : in  STD_LOGIC_VECTOR(31 downto 0);
           b : in  STD_LOGIC_VECTOR(31 downto 0);
           alu_out : out  STD_LOGIC_VECTOR(31 downto 0) := (others => '0')
           );
end adder;

architecture Behavioral of adder is
  signal result_ext:STD_LOGIC_VECTOR(32 downto 0) := (others => '0');
  signal result:STD_LOGIC_VECTOR(31 downto 0)     := (others => '0');
begin

  process (a,b)
  begin
    result_ext <= std_logic_vector(signed('0' & a) + signed('0' & b));
    result     <= result_ext(result'left downto 0);

    alu_out <= result;
  end process;
end Behavioral;

和测试台：

-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS         

    signal a : STD_LOGIC_VECTOR(31 downto 0);
    signal b : STD_LOGIC_VECTOR(31 downto 0);
    signal alu_out : STD_LOGIC_VECTOR(31 downto 0);
  BEGIN
    ADDER : entity work.adder port map(
      a => a,
      b => b,
      alu_out => alu_out
    );



  --  Test Bench Statements
     tb : PROCESS
     BEGIN

        a <= B"0000_0000_0000_0000_0000_0000_0111_1010";
        b <= B"0000_0000_0000_0000_0000_0000_0000_1011";

        wait for 100 ns; -- wait until global set/reset completes

        report "alu_out = " & integer'image(to_integer(signed(alu_out)));

        wait; -- will wait forever
     END PROCESS tb;
  --  End Test Bench 

  END;

我得到报告输出：

Finished circuit initialization process.
at 100 ns: Note: alu_out = 0 (/testbench/).

如果我不初始化结果信号，我会得到未定义。所以问题是我最终没有得到结果。

我使用iSim和Xilinx。

此外，如果有人有一些关于 VHDL 的简短有效材料的良好链接，请随时发布。

4

2 回答 2

2

以彼得的代码和：

  • 更新输入宽度的灵活性
  • 只是numeric_std
  • 保持进位

给出了这个：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity adder is
    generic (width : integer := 32)
    Port ( a       : in  signed(width-1 downto 0);
           b       : in  signed(width-1 downto 0);
           alu_out : out signed(width downto 0) := (others => '0');
           );
end adder;

architecture synth of adder is
begin
  process (a,b)
  begin
    alu_out <= resize(a,alu_out'length) + b;
  end process;
end Behavioral;
于 2012-05-15T12:27:48.373 回答
1

问题是您正在使用信号result以及result_ext何时需要它们对该过程周期的直接价值。变量会立即更新，您可以在流程的当前周期中访问它们的值。

试试这个，我认为它可以解决您遇到的问题：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity adder is
    Port ( a : in  STD_LOGIC_VECTOR(31 downto 0);
           b : in  STD_LOGIC_VECTOR(31 downto 0);
           alu_out : out  STD_LOGIC_VECTOR(31 downto 0) := (others => '0')
           );
end adder;

architecture Behavioral of adder is


begin

  process (a,b)
    variable result_ext:STD_LOGIC_VECTOR(32 downto 0) := (others => '0');
    variable result:STD_LOGIC_VECTOR(31 downto 0);
  begin
    result_ext := std_logic_vector(signed('0' & a) + signed('0' & b));
    result     := result_ext(result'left downto 0);

    alu_out <= result;
  end process;
end Behavioral;

至于阅读材料，VHDL Cookbook 还不错：VHDL Cookbook

于 2012-05-15T09:17:39.767 回答