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我正在尝试使用 xilinix 10.1 实现有限状态机标识符我在以前的问题中看到了这些错误，但答案不包括我的问题。我不是在寻找答案，而是在寻找 FFd1 部分的含义

产生以下错误

WARNING:Xst:1293 - FF/Latch <machine1/current_state_FFd1> has a constant value of 0 in block <Main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <machine1/current_state_FFd2> has a constant value of 0 in block <Main>. This FF/Latch will be trimmed during the optimization process.

这是我的代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity M_1 is
    Port ( x : in  STD_LOGIC;
       clk : in  STD_LOGIC;
       state : out  integer range 0 to 5 := 0;
       z : out  STD_LOGIC );
end M_1;

architecture Behavioral of M_1 is

 type state_type is (A, B, C, D);
 signal next_state, current_state: state_type := A;

begin

process(clk) is
begin
if (clk = '1' and clk'event) then
    current_state <= next_state;
end if;
end process;

process(x,current_state)
begin
case current_state is
    when A =>
        if(x='0') then
            next_state <= B;
            z <='0';
        elsif(x='1') then
            next_state <= C;
            z <='1';            
        end if;
    when B =>
        if(x='0') then
            next_state <= C;
            z <='1';
        elsif(x='1') then
            next_state <= D;
            z <='0';            
        end if;
    when C =>
        if(x='0') then
            next_state <= A;
            z <='0';
        elsif(x='1') then
            next_state <= D;
            z <='1';            
        end if;
    when D =>
        if(x='0') then
            next_state <= B;
            z <='0';
        elsif(x='1') then
            next_state <= C;
            z <='0';            
        end if;
    end case;
end process;

process (current_State) is
begin
    case current_state is
    when A =>
        state <=0;
    when B =>
        state <=1;
    when C =>
        state <=2;
    when D =>
        state <=3;
    end case;
end process;

end Behavioral;

谁能告诉我

  • current_state_FFd1 和 current_State_1 有什么区别？
  • 我该如何解决这个错误？

提前致谢

4

1 回答 1

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CAD 工具将“current_state”信号映射到 2 位触发器原语上。触发器看起来类似于FD16CE 原语，如图所示。

触发器将采用 2 个数据输入（current_state_FFd1 和 current_state_FFd2）和一个时钟，并产生两个数据输出（current_state_FFq1 和 current_state_FFq2）。输入确定在下一个时钟沿采样的 current_state 信号的值，输出反映当前状态。

您看到的消息表明 CAD 工具可以证明“current_state”永远不会从“00”编码（枚举类型中的“A”）改变，因此可以使用硬连线优化触发器“00”的输出。

您发布的 VHDL 看起来很合理——“x”输入的变化应该会导致 current_state 的变化。我敢打赌，“x”输入在更高级别的 VHDL（或您的测试台）中以某种方式硬连线到 0。

于 2012-05-15T16:24:06.847 回答