0

编码：

        library IEEE;
        use IEEE.std_logic_1164.all;
        use ieee.numeric_std.all;
        use ieee.std_logic_unsigned.all;
        entity decoder10 is 
        port( in_data:  in STD_LOGIC_VECTOR (7 downto 0);
                clk : in STD_LOGIC;
                out_data:  out STD_LOGIC_VECTOR (7 downto 0));
        end decoder10;

        architecture behavioral of decoder10 is
        signal int_bus1 : STD_LOGIC_VECTOR (63 downto 0);
        signal int_bus2 : STD_LOGIC_VECTOR (63 downto 0);
        signal int_bus3 : STD_LOGIC_VECTOR (31 downto 0);
        signal lower : STD_LOGIC_VECTOR (31 downto 0);
        signal higher : STD_LOGIC_VECTOR (31 downto 0);
        signal intermid : STD_LOGIC_VECTOR (31 downto 0);
        signal curr_key : STD_LOGIC_VECTOR (31 downto 0);
        signal got_data: std_logic;      --data written in    
        signal variable_test: std_logic:= '0';      
        signal n_ready: std_logic; --code assembled
        signal k_ready: std_logic; --key selected
        signal k_added: std_logic; --key added
        signal sub_ready: std_logic; --blocks substituted
        signal sh_ready: std_logic; --shift done
        signal xor_ready: std_logic; --xor done
        signal out_ready: std_logic; --ready for output
        signal sent_data: std_logic; --data written out  
        signal start_again: std_logic; --start the main step again
        type arr is array (0 to 15) of std_logic_vector(31 downto 0);
        type key is array (0 to 7) of std_logic_vector(31 downto 0);
        type key_num is array (0 to 31) of integer;
        signal key_it : key_num := (0,1,2,3,4,5,6,7,
                                             7,6,5,4,3,2,1,0,
                                             7,6,5,4,3,2,1,0,
                                             7,6,5,4,3,2,1,0);

        signal tab : arr := (X"00000001",
                                    X"00000002",
                                    X"00000003",
                                    X"00000004",
                                    X"00000005",
                                    X"00000006",
                                    X"00000007",
                                    X"00000008",
                                    X"00000009",
                                    X"0000000a",
                                    X"0000000b",
                                    X"0000000c",
                                    X"0000000d",
                                    X"0000000e",
                                    X"0000000f",
                                    X"00000000");  

        signal tab_key : key := (X"00000007",
                                         X"00000006",
                                         X"00000005",
                                         X"00000004",
                                         X"00000003",
                                         X"00000002",
                                         X"00000001",
                                         X"00000000");

        component adder is 
        port(   dataa       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                datab       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                result      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
        END component;

        begin

        add1: adder
            port map (lower, curr_key, int_bus3);

        process (clk, in_data)
        variable i: INTEGER := 0;
        variable j: INTEGER := 0;
        variable k: INTEGER := 0;


        begin
          -- assembling input code into one piece
          if (rising_edge(clk)) then
              if (i<8) then
                 int_bus1(63 downto 56)<=in_data;
                got_data <= '1';
                n_ready <= '0';
                 if (got_data = '1') then 
                     --shift right 8 bits 
                     int_bus1(55 downto 0) <= int_bus1(63 downto 8);
                     i := i + 1;
                     got_data <= '0';
                 end if;
              end if;

                 if (i = 8 and n_ready = '0' and out_ready = '0') then
                     lower<=int_bus1(31 downto 0);
                     higher<=int_bus1(63 downto 32);
                     n_ready <= '1';
                     start_again <= '1';
                 end if;
          end if; 



          if (n_ready ='1') then
          -- base encryption step
             if (rising_edge(clk)) then
             if (j <32 and start_again = '1') then
             -- key/step dependence
                 curr_key <= tab_key(key_it(j));
                k_ready <= '1';
                start_again <= '0';
             end if;   

             if (k_ready = '1') then 
                    lower <= curr_key + lower;
                    k_added <= '1';
                    k_ready <='0';
             end if;

             if (k_added = '1') then
                    --block substitution
                    lower(3 downto 0) <= tab(CONV_INTEGER(lower(3 downto 0)))(3 downto 0);
                    lower(7 downto 4) <= tab(CONV_INTEGER(lower(7 downto 4)))(7 downto 4);
                    lower(11 downto 8) <= tab(CONV_INTEGER(lower(11 downto 8)))(11 downto 8);
                    lower(15 downto 12) <= tab(CONV_INTEGER(lower(15 downto 12)))(15 downto 12);
                    lower(19 downto 16) <= tab(CONV_INTEGER(lower(19 downto 16)))(19 downto 16);
                    lower(23 downto 20) <= tab(CONV_INTEGER(lower(23 downto 20)))(23 downto 20);
                    lower(27 downto 24) <= tab(CONV_INTEGER(lower(27 downto 24)))(27 downto 24);
                    lower(31 downto 28) <= tab(CONV_INTEGER(lower(31 downto 28)))(31 downto 28);
                    sub_ready <= '1';
                    k_added <= '0';
             end if;    

             if (sub_ready = '1') then
                  --shift 11 bits right cyclically
                    lower(31 downto 21) <= lower(10 downto 0);
                    lower(20 downto 0) <= lower(31 downto 11);
                    sh_ready<= '1';
                    sub_ready <= '0';
             end if;

             if (sh_ready = '1') then
                    higher <= lower xor higher;
                    lower <= higher;
                    sh_ready<= '0';
                    j:=j+1;
                    start_again <= '1';
                    out_ready <= '0'; 
              end if;
              end if; 
             end if;     

         if (rising_edge(clk)) then
              if (j = 32 and out_ready = '0') then
                j:=j+1;
                variable_test <= '1'; --artifact of testing the behavior of variables
              end if;   


         end if;
          -- assembling output code into one piece
          if (rising_edge(clk)) then  
            if (out_ready = '0' and variable_test = '1') then
                 int_bus2 (63 downto 32) <= higher;
                 int_bus2 (31 downto 0) <= lower;
                 out_ready <= '1';
                 n_ready <= '0';
            end if;

             if (out_ready = '1' and k<8) then
                 out_data<=int_bus2(7 downto 0);
                 sent_data <= '1';
                 if (sent_data ='1') then 
                    --shift right 8 bits 
                     int_bus2(55 downto 0) <= int_bus2(63 downto 8);
                     k := k + 1;
                     sent_data <= '0';
                 end if;
            end if;
         end if;
        end process; 
        end behavioral;

我收到以下错误：

错误 (10821)：decoder10.vhd(106) 处的 HDL 错误：无法推断寄存器，start_again因为它的行为与任何受支持的寄存器模型都不匹配
信息 (10041)：推断解码器start_again10.vhd(75) 处的锁存器
错误 (10821) ：decoder10.vhd(106) 处的 HDL 错误：无法推断寄存器，higher[0]因为它的行为与任何支持的寄存器模型都不匹配
信息 (10041)：推断出解码器higher[0]10.vhd(75) 的锁存器（
前 18 位继续“更高”的）

为什么不能合成？为什么不能只higher推断出前 18 位？

4

2 回答 2

1

这很可能是因为您的时钟启用比您的时钟具有更高的优先级，并且不存在允许这样做的 FPGA 硬件。每当您为综合编写代码时，您都需要考虑这是否真的可以映射到底层硬件。所以而不是

if (n_ready ='1') then
  -- base encryption step
  if (rising_edge(clk)) then
    (...)

尝试：

if(rising_edge(clk)) then
  if(n_ready = '1') then
    (...)

看看Get your priority right - 它是为 Xilinx FPGA 编写的，但我猜类似的东西也适用于其他品牌。

于 2012-05-01T06:15:02.307 回答
0

第一个答案，通过 sonicwave 在所有架构中都不是严格正确的，尽管我认为在这种情况下是正确的。
if 后跟边沿可以通过门控时钟实现，但这并不是一个好主意，或者它在所有类型的 FPGA 或 CPLD 架构中都受支持。

一些提示：将 tab 和 tab_key 更改为常量。它们从未被分配，因此不需要信号。使它们成为信号可能意味着它们在某些架构中被统一化。

整个事情应该使用流程，而不是使用顺序逻辑。这会导致“推断锁存器”错误，这取决于代码 start_again 的路径可能会也可能不会被写入。为避免推断锁存器，请确保通过所有路径写入信号或在进程内计时。

您需要记住，VHDL 不是一种编程语言，它是一种描述语言。除非系统是同步的，否则所有行都会同时执行。例如，在第 147 行，您有两条线同时操作更高和更低。

如果您告诉我您要达到的目标，我可以为您重新编写它。

于 2012-05-02T08:03:41.103 回答