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我有可变数量的模块通过 a 链接到另一个模块signal bus : std_logic_vector(NUM-1 downto 0)，每个组件使用 8 位，因此：

bus(7 downto 0) = first module
bus(15 downto 8) = second module

至于创建实例和进行端口映射，这很容易通过

INST: for i in 0 to NUM-1 generate
         Inst_module port map ( bus => bus(i*8+7 downto i*8) );
       end generate INST;

我的问题： 我希望能够通过 FSM 与每个模块交互（因为它也需要做一些其他事情），所以希望能够“生成”以下代码，而不是必须写出每个手动状态（signal empty : std_logic_vector(NUM-1 downto 0)每个模块的状态标志在哪里）

 type state_type is (st0_idle, st1_work0, st1_work1 --,etc.)
 signal state : state_type;
 begin
 process(empty)
   begin
     if RESET = '1' then
        --reset FSM
        state <= st0_idle;
     else
       if CLK'event and CLK='1' then
         case state is
           when st0_idle =>
             if empty(0) = '0' then
               state <= st1_work0;
             elsif empty(1) = '1' then
               state <= st1_work1;
             --etc.
             end if;             
           when st1_work0 =>
             bus(7 downto 0) <= SOMETHING;
             state <= st0_idle;
           when st1_work1 =>
              bus(15 downto 8) <= SOMETHINGELSE;
              state <= st0_idle;
            --etc..
       end if;
     end if;
end process;

如您所见，有很多重复。但是我不能简单地把一个for-generate放在箱子里，那我该怎么办呢？

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1 回答 1

4

使具有状态机的流程更具可读性的一种好方法是将通用代码合并到流程中定义的过程中。例如：

process (empty) is

  procedure assign_something (
    index      : natural;
    something  : std_logic_vector(7 downto 0)
    next_state : state_type
  ) is
  begin
    bus(index*8+7 downto index*8) <= something;
    state <= next_state;
  end procedure;

begin
  wait until rising_edge(clk);
  case state is
    when st0_idle  => ...
    when st1_work0 => assign_something(0, something,      st0_idle);
    when st1_work1 => assign_something(1, something_else, st0_idle);
    -- ... etc ...
  end case;
  if reset = '1' then
    state <= st0_idle;
  end if;
end procedure;

希望你明白这一点。根据状态机结构的规则性，您可能还希望将与每个索引对应的枚举状态变量替换为您跟踪的简单计数或索引变量以及命名状态。

这完全取决于您，但是无论您怎么做，只要有可能就使用过程来分解出通用代码，这可能会使您的 VHDL 更易于使用。

应用此更改将使代码看起来像这样：

architecture ...

type state_type is (st_idle, st_work);
signal state : state_type;
signal index : integer range 0 to NUM-1;

...
begin
...

process (empty) is

  procedure assign_something (
    index      : natural;
    something  : std_logic_vector(7 downto 0)
    next_state : state_type
  ) is
  begin
    bus(index*8+7 downto index*8) <= something;
    state <= next_state;
  end procedure;

begin
  wait until rising_edge(clk);
  case state is
    when st_idle  => 
      for i in 0 to NUM-1 loop
         if empty(i) = '1' then
           index := i;
           exit;
         end if;
      end loop;
    when st_work => assign_something(index, something, st_idle);
  end case;
  if reset = '1' then
    state <= st_idle;
  end if;
end procedure;

显然这必须改变以完全匹配你想要做的...... =）

于 2011-11-08T22:04:19.383 回答