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这是一个简单的计数器verilog代码，它转储一个vcd文件。它已从这里改编。

下面的代码运行 20 个周期。但是，如果我取消注释 verilog 代码中的 $stop 行，那么在模拟过程中会出现此错误：

%Error: counter.v:23: Verilog $stop
Aborting...
Aborted (core dumped)

如何解决这个问题，以便我可以在 $stop 上优雅地退出？我尝试用 gotStop() 替换 gotFinish()，但这给出了这个错误：

"gotStop() is not a member of Verilated"

这是 tb.cpp，顶部还有编译/运行指令：

// generate: verilator -Wall --cc --trace counter.v --exe tb.cpp
// compile: make -C obj_dir -f Vcounter.mk Vcounter
// run: obj_dir/Vcounter

#include "Vcounter.h"
#include "verilated.h"
#include "verilated_vcd_c.h"

int main(int argc, char **argv, char **env) {
  int i;
  int clk;
  Verilated::commandArgs(argc, argv);
  Vcounter* top = new Vcounter;
  Verilated::traceEverOn(true);
  VerilatedVcdC* tfp = new VerilatedVcdC;
  top->trace (tfp, 99);
  tfp->open ("counter.vcd");
  top->clk = 1;
  top->rst = 1;
  top->cen = 0;
  top->wen = 0;
  top->dat = 0x55;
  // run simulation for 20 clock cycles
  for (i=0; i<20; i++) {
    top->rst = (i < 2);
    tfp->dump (2*i);
    top->clk = !top->clk; // negedge
    top->eval ();
    tfp->dump (2*i+1);
    top->clk = !top->clk; // posedge
    top->eval ();
    top->cen = (i > 5);
    top->wen = (i == 10);
    if (Verilated::gotFinish()) break;
  }
  tfp->close();
  exit(0);
}

这是counter.v：

module counter #(parameter WIDTH = 8)(
  input  wire             clk,
  input  wire             rst,
  input  wire             cen,
  input  wire             wen,
  input  wire [WIDTH-1:0] dat,
  output reg  [WIDTH-1:0] o_p,
  output reg  [WIDTH-1:0] o_n
);

integer icount;

initial begin
    icount = 0;
end

always@(posedge clk) begin
    icount <= icount + 1;
    if(icount==10) $display("working till 10");
    //if(icount==12) $stop;
end

always @ (posedge clk or posedge rst)
if (rst) o_p <= {WIDTH{1'b0}};
else     o_p <= wen ? dat : o_p + {{WIDTH-1{1'b0}}, cen};


always @ (negedge clk or posedge rst)
if (rst) o_n <= {WIDTH{1'b0}};
else     o_n <= wen ? dat : o_n + {{WIDTH-1{1'b0}}, cen};

endmodule
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