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我正在尝试熟悉 verilog 中的（子）模块，但遇到了我无法解释的错误。我有这两个文件：

顶部.v：

parameter CLOCK_FREQUENCY = 24'd12_000_000;
parameter TRANSMISSION_LENGTH = 32;

`include "serialtx.v"

module top(
        input clk,
        output txd
    );
    
    reg wr;
    reg [TRANSMISSION_LENGTH - 1:0] data;
    reg busy;
    
    initial wr = 1'b0;
    initial data = 0;
    
    serialtx tx(
        .i_clk(clk),
        .i_wr(wr),
        .i_data(data),
        .o_txd(txd),
        .o_busy(busy)
    );
    
endmodule

序列号.v：

module serialtx(
        input i_clk,
        input i_wr,
        input [TRANSMISSION_LENGTH - 1:0] i_data,
        output wire o_txd,
        output wire o_busy
    );
    
    initial o_busy = 1'b0;
    initial o_txd = 1'b1;
    
    always @(posedge i_clk)
    begin
        if (i_wr && !o_busy) begin
            o_busy <= 1'b1;
            o_txd <= 1'b0;
        end
    end
    
endmodule

要将它们上传到我的 ECP5，我使用以下命令流：

yosys -p "synth_ecp5 -json top.json" top.v
nextpnr-ecp5 --json top.json --textcfg top_out.config --um5g-85k --package CABGA381 --lpf ecp5evn.lpf
ecppack --svf top.svf top_out.config top.bit
sudo --preserve-env=PATH env openocd -f ./ecp5.cfg -c "transport select jtag; init; svf top.svf; exit"

它上传并正常工作（有一个 LED 连接到 txd，它根据serialtx.vinitial o_txd = 1'bx中的语句打开/关闭，其中 x 可以是 1 或 0）。

但是，当我尝试模拟 verilog 代码时，会出现一些错误。我无法解释这些错误，因为错误消息对我来说是中文的，并且实际的实现是有效的。这是我使用的命令：

verilator -Wall --trace -cc top.v

这是生成的错误日志：

%Error-PROCASSWIRE: serialtx.v:9:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o_busy'
                                   : ... In instance top.tx
    9 |  initial o_busy = 1'b0;
      |          ^~~~~~
                    top.v:2:35: ... note: In file included from top.v
                    ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.215
%Error-PROCASSWIRE: serialtx.v:10:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o_txd'
                                    : ... In instance top.tx
   10 |  initial o_txd = 1'b1;
      |          ^~~~~
                    top.v:2:35: ... note: In file included from top.v
%Error-PROCASSWIRE: serialtx.v:15:4: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o_busy'
                                   : ... In instance top.tx
   15 |    o_busy <= 1'b1;
      |    ^~~~~~
                    top.v:2:35: ... note: In file included from top.v
%Error-PROCASSWIRE: serialtx.v:16:4: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o_txd'
                                   : ... In instance top.tx
   16 |    o_txd <= 1'b0;
      |    ^~~~~
                    top.v:2:35: ... note: In file included from top.v
%Warning-UNUSED: top.v:13:6: Signal is not used: 'busy'
                           : ... In instance top
   13 |  reg busy;
      |      ^~~~
                 ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: top.v:1:11: Parameter is not used: 'CLOCK_FREQUENCY'
                           : ... In instance top
    1 | parameter CLOCK_FREQUENCY = 24'd12_000_000;
      |           ^~~~~~~~~~~~~~~
%Warning-UNUSED: serialtx.v:4:37: Signal is not used: 'i_data'
                                : ... In instance top.tx
    4 |   input [TRANSMISSION_LENGTH - 1:0] i_data,
      |                                     ^~~~~~
                 top.v:2:35: ... note: In file included from top.v
%Error: Exiting due to 4 error(s), 3 warning(s)
        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

[编辑] 据我了解，程序分配是寄存器值的更新。此外，默认情况下，输出定义为电线而不是寄存器。因此，模拟引发错误是有道理的。但是这个硬件怎么可能在实现中运行呢？

4

1 回答 1

1

类型的信号wire不能按程序编写（例如，在always和initial块中）。您的综合工具应该在这里抛出错误（就像模拟器一样），大概它只是将信号视为reg.

要解决此问题，请将输出端口从线更改为 reg，如下所示：

output reg o_txd,
output reg o_busy
于 2021-12-08T15:24:22.020 回答