我有一个很大的设计,包括一个测试台、一些测试电路和被测电路本身。我使用 modelsim 来模拟设计,我想要一个模拟转储。有人建议我使用以下命令生成转储:
vcd file myvcd1.vcd
vcd add -r /sim_minimips/*
它似乎可以工作,但我想要的是仅为被测电路生成转储。
我尝试使用相同的命令来指定我想要考虑的文件的名称:
vcd file myvcd2.vcd
vcd add -r /minimips/*
但产生了以下错误:
Error vsim 3561 No object matching minimips
我不明白这个错误,即使这是隔离子部分的正确程序,我也不确定。
有谁知道该怎么做或知道我在哪里可以获得有关此值更改转储的简单教程?
我附上我的测试台实体:
library IEEE;
use IEEE.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.pack_mips.all;
entity sim_minimips is
end;
architecture bench of sim_minimips is
component minimips is
port (
clock : in std_logic;
reset : in std_logic;
ram_req : out std_logic;
ram_adr : out bus32;
ram_r_w : out std_logic;
ram_data : inout bus32;
ram_ack : in std_logic;
it_mat : in std_logic
);
end component;
component ram is
generic (mem_size : natural := 256;
latency : time := 10 ns);
port(
req : in std_logic;
adr : in bus32;
data_inout : inout bus32;
r_w : in std_logic;
ready : out std_logic
);
end component;
component rom is
generic (mem_size : natural := 256;
start : natural := 0;
latency : time := 10 ns);
port(
adr : in bus32;
donnee : out bus32;
ack : out std_logic;
load : in std_logic;
fname : in string
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic;
signal it_mat : std_logic := '0';
-- Connexion with the code memory
signal load : std_logic;
signal fichier : string(1 to 7);
-- Connexion with the Ram
signal ram_req : std_logic;
signal ram_adr : bus32;
signal ram_r_w : std_logic;
signal ram_data : bus32;
signal ram_rdy : std_logic;
begin
U_minimips : minimips port map (
clock => clock,
reset => reset,
ram_req => ram_req,
ram_adr => ram_adr,
ram_r_w => ram_r_w,
ram_data => ram_data,
ram_ack => ram_rdy,
it_mat => it_mat
);
U_ram : ram port map (
req => ram_req,
adr => ram_adr,
data_inout => ram_data,
r_w => ram_r_w,
ready => ram_rdy
);
U_rom : rom port map (
adr => ram_adr,
donnee => ram_data,
ack => ram_rdy,
load => load,
fname => fichier
);
clock <= not clock after 20 ns;
reset <= '0', '1' after 5 ns, '0' after 70 ns;
ram_data <= (others => 'L');
process
variable command : line;
variable nomfichier : string(1 to 3);
begin
write (output, "Enter the filename : ");
readline(input, command);
read(command, nomfichier);
fichier <= nomfichier & ".bin";
load <= '1';
wait;
end process;
-- Memory Mapping
-- 0000 - 00FF ROM
process (ram_adr, ram_r_w, ram_data)
begin -- Emulation of an I/O controller
ram_data <= (others => 'Z');
case ram_adr is
when X"00001000" => -- program an interrupt after 1000ns
it_mat <= '1' after 1000 ns;
ram_rdy <= '1' after 5 ns;
when X"00001001" => -- clear interrupt line on cpu
it_mat <= '0';
ram_data <= X"FFFFFFFF";
ram_rdy <= '1' after 5 ns;
when others => ram_rdy <= 'L';
end case;
end process;
end bench;
干杯,斯特