0

我正在尝试在 Nexys4 DDR 上设计秒表并收到以下错误：

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets en_IBUF] >

    en_IBUF_inst (IBUF.O) is locked to IOB_X0Y82
     and en_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

这是我的代码：

----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std;


entity cronometru is
     Port (clock: in std_logic;
            directie: in std_logic;
            SW: in std_logic_vector(14 downto 0);
            LED: inout std_logic_vector(14 downto 0);
            en: in std_logic;
            load: in std_logic;
            reset: in std_logic;
            AN: out std_logic_vector(7 downto 0);
            afis: out std_logic_vector(6 downto 0));
end cronometru;

architecture crono of cronometru is
signal bcd: std_logic_vector(3 downto 0);
signal bcd1: std_logic_vector(3 downto 0);
signal bcd2: std_logic_vector(3 downto 0);
signal bcd3: std_logic_vector(3 downto 0);
signal bcd4: std_logic_vector(3 downto 0);
signal bcd5: std_logic_vector(3 downto 0);
signal refresh: std_logic_vector(2 downto 0);
signal temp: std_logic:='1';
signal copiat: std_logic_vector(14 downto 0);
signal zecimal: integer range 0 to 32767;
signal secunde: integer range 0 to 60;
signal zeci_secunde: integer range 0 to 5;
signal unitati_secunde: integer range 0 to 9;
signal minute: integer range 0 to 60;
signal zeci_minute: integer range 0 to 5;
signal unitati_minute: integer range 0 to 9;
signal unitati_ore: integer range 0 to 9;
signal count: std_logic_vector(14 downto 0);
signal enable: std_logic:='0';
begin

process(bcd) --here i display a digit
begin
case bcd is
when "0000" => afis <= "0000001"; -- "0"
when "0001" => afis <= "1001111"; -- "1"
when "0010" => afis <= "0010010"; -- "2"
when "0011" => afis <= "0000110"; -- "3"
when "0100" => afis <= "1001100"; -- "4"
when "0101" => afis <= "0100100"; -- "5"
when "0110" => afis <= "0100000"; -- "6"
when "0111" => afis <= "0001111"; -- "7"
when "1000" => afis <= "0000000"; -- "8"
when "1001" => afis <= "0000100"; -- "9"
when others => afis <= "0110110";
end case;
end process;



process(en) --  here i handle the stop signal 
begin
if (en'event and en='1') then
    enable<=not enable;
end if;
end process;



process(clock)--here i slow down the clock 
variable cnt: integer:=0;
begin
if(clock'event and clock='1') then
    refresh<=refresh+1;
    cnt:=cnt+1;
    if(cnt=50000001)then
        temp<='0';
    end if;
    if(cnt=100000001) then
        temp<='1';
        cnt:=1;
    end if;
end if;
end process;



process(temp, reset, enable,directie,load)
begin
if reset='1' then
    count<=(others=>'0');
elsif load='1' then 
    count<=SW;
elsif (temp='1' and temp'event) then
    if(directie='0' and enable='1') then
        count<=count+1;
    elsif (directie='1' and enable ='1') then 
        count<=count-1;
    else count<=count;
    end if;
end if;
end process;
LED<=count;




process(refresh)
begin --here i find the value of each digit using the number of seconds
copiat<=LED;
zecimal<=conv_integer(unsigned(copiat));
unitati_ore<=zecimal/3600;
minute<=(zecimal mod 3600)/60;
secunde<=(zecimal mod 3600) mod 60;
unitati_minute<=minute mod 10;
zeci_minute<=minute/10;
unitati_secunde<=secunde mod 10;
zeci_secunde<=secunde/10;
bcd1<=conv_std_logic_vector(unitati_secunde,4);
bcd2<=conv_std_logic_vector(zeci_secunde,4);
bcd3<=conv_std_logic_vector(unitati_minute,4);
bcd4<=conv_std_logic_vector(zeci_minute,4);
bcd5<=conv_std_logic_vector(unitati_ore,4);
case refresh is -- here i select what digit to be displayed
when "000"=> AN<="11111110";
            bcd<=bcd1;
when "001"=> AN<="11111101";
            bcd<=bcd2;
when "010"=> AN<="11111011";
            bcd<=bcd3;
when "011"=> AN<="11110111";
             bcd<=bcd4;
when "100"=> AN<="11101111";
             bcd<=bcd5;
when "101"=> AN<="11111011";
             bcd<=bcd3;
when "110"=> AN<="11110111";
             bcd<=bcd4;
when "111"=> AN<="11101111";
             bcd<=bcd5;                                                 
when others => AN<="11111111";
                bcd<="0000";
end case;
end process;
end crono;

我不明白为什么我会遇到这个问题，因为在我以前的实现中，我以完全相同的方式使用时钟。有人可以帮助我吗？

以下是引用时钟的约束文件中的代码：

set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clock }]; 
#IO_L12P_T1_MRCC_35 Sch=clock
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clock}];
4

0 回答 0