这是 vhdl 中的代码:
library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER_TWO is
port
(
SW : in std_logic_vector(2 downto 1);
LD : out std_logic_vector(4 downto 1)
);
end DECODER_TWO;
architecture MY_FIRST_DECODER of DECODER_TWO is
begin
with SW select
LD <= "1110" when "00",
LD <= "1101" when "01",
LD <= "1011" when "10",
LD <= "0111" when "11",
LD <= "1111" when others;
end MY_FIRST_DECODER;
当我尝试编译这个非常简单的 2 到 4 位解码器时,无论我做什么,我都会收到错误消息
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(15): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(16): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(17): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(18): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(19): VHDL Compiler exiting
我看不到或不明白问题出在哪里,因为我在第一行没有收到“<=”的错误,只有第 2、3、4 和 5 行。