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为所有制造的设备提供 linux 保留的 io 端口号。

我有英特尔内置网卡之类的设备。或我拥有的其他用于 wifi (usb) 的 realtek 设备。在 github 上的 linux 存储库中，设备驱动程序使用特定的 io 端口进行注册。内核将这些端口分配给设备驱动程序。设备驱动程序通常使用对 request_region 函数的调用来请求端口。所以对于某些以太网设备，它要求如下

    for (id_port = 0x110 ; id_port < 0x200; id_port += 0x10)
     {
    if (!request_region(id_port, 1, "3c509-control")) 
    continue;
    outb(0x00, id_port);
    outb(0xff, id_port);
    if (inb(id_port) & 0x01)
    break;
    else
    release_region(id_port, 1);
    }

上面以0x110to开头0x200，内核可以在此范围内将任何端口分配给驱动程序并出现在 /proc/ioports 文件中，这意味着驱动程序在成功返回时正在使用该 io 端口request_region。

问题：所以我的问题是 linux 是否为所有可用于内核 5.7 或最新内核版本的制造设备分配了 io 端口？

问题：如果我想为任何设备编写设备驱动程序怎么办。如何找到要请求的 io 端口号范围。我不希望我必须查看内核代码并找到更相似的驱动程序端口范围。所以我怎样才能找到那个io端口号范围。如何实现编写设备驱动程序所需的第一步（任何设备。无论是 wifi 互联网设备还是以太网设备）

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问题：所以我的问题是 linux 是否为所有可用于内核 5.7 或最新内核版本的制造设备分配了 io 端口？

不。

问题：如果我想为任何设备编写设备驱动程序怎么办。如何找到要请求的 io 端口号范围。

你向用户索要它。毕竟是用户使用 ISA 卡上的跳线设置它们。

这是一张旧 Sound Blaster 卡的照片（取自维基百科，我现在懒得在地下室翻找）。我在图片中突出显示了一个特定区域：

突出显示端口跳线的 Sound Blaster 卡

我强调的那个跳线头：那是端口配置跳线。作为用户，您实际上将两个引脚与跳线连接器连接起来，并将来自卡连接器的特定地址线连接到卡其余部分的电路。该地址线是 AT 总线端口 I/O 方案的一部分。用户设置此跳线，记下数字，然后告诉司机它被设置为哪个数字。这就是 AT 风格的 I/O 端口。

Or the driver uses one of the well known port numbers for specific hardware (like network controllers) that dates back to the era, where ISA style ports were still are thing. Also there's old ISA-P'n'P where the BIOS and the add-in cards would negotiate the port assignments at power up, before the OS even started. You can read those port numbers with the ISA-P'n'P API provided by the kernel.

We no longer use this kind of hardware in practice! Except for legacy and retro computing purposes.

Over a quarter of century ago, the old AT / ISA bus was superseeded with PCI. Today we use PCIe which, from the point of view of software still looks like PCI. One of the important things about PCI was, that it completely dropped the whole concept of ports.

With ISA what you had were 8 data lines and 16 address lines, plus two read/write enable lines, one for memory mapped I/O and one for port I/O. You can find the details here https://archive.is/3jjZj. But what happens when you're reading from say, port 0x0104, it would physically set the bit pattern of 0x0104 to the address lines on the ISA bus, pull low the read enable line, and then read the voltage level on the data lines. And all of that is implemented as an actual set of instructions of the x86: https://c9x.me/x86/html/file_module_x86_id_139.html

Now look at the PCI bus: There's no longer separate data and address lines. Instead read/write commands would be sent, and everything happens through memory mappings. PCI devices have something called a BAR: a Base Address Register. This is configured by the PCI root complex and assigns the hardware the region of actual physical bus addresses where it appears. The OS has to get those BAR information from the PCI root complex. The driver uses the PCI IDs to have the hardware discovered and the BAR information told to it. It can then do memory reads/writes to talk to the hardware. No I/O ports involved. And that is just the lowest level. USB and Ethernet happen a lot further up. USB is quite abstract, as is Ethernet.

您的另一个问题寻找 Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz 的驱动程序开发人员数据表表明，您对实际发生的事情有一些严重的误解。您询问的是 USB 设备和以太网端口。它们都不会以任何方式直接与计算机的这一部分交互。

你的问题本身很有趣。但是我们在这里也遇到了一个巨大的 XYZ 问题；它比 XY 问题更糟糕；你问的是 X，虽然你想解决 Y。但 Y 甚至不是你首先要处理的问题。

你显然很聪明，而且很好奇，我对此表示赞赏。但我必须告诉你，你必须回溯很多，以澄清你的一些误解。

于 2021-01-03T10:41:49.880 回答