我会尽量做到完整和具体：
恩智浦 LPC1756 Cortex-M3。Eclipse Helios 使用 Codesourcery ARM 工具链和 OpenOCD 进行调试。JTAG 是 Olimex ARM-USB-OCD。操作系统是 Windows 7 64 位。
我相信我现在已经解决了闪存上传方面的问题。编程后，我让脚本执行 dump_image 并且转储的图像看起来大致正确。目前我有验证问题需要解决，但在这个阶段，我的 JTAG 设置似乎正在工作，并且我正在与 '1756 成功通信。
但是，当我尝试调试时，我遇到了问题。首先，我的 cfg 文件，从我的目标设备 cfg 文件开始：
# NXP LPC1756 Cortex-M3 with 256kB Flash and 32kB SRAM
debug_level 2
# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
#source [find swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1756
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
$_TARGETNAME configure -work-area-backup 0
#$_TARGETNAME configure -endian $_ENDIAN
#$_TARGETNAME configure -variant ARMv7
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#reset_config srst_only
#reset_config trst_and_srst srst_pulls_trst
# LPC1756 has 256kB of flash memory, managed by ROM code (including a
# boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
jtag_khz 50
#$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
#MEMMAP - set user mode
# mww 0x400FC040 0x01
#}
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
#armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
#mwb 0xE01FC040 0x01
mwb 0x400FC040 0x01
#mwb 0xE000ED08 0x00
}
现在，我的调试 cfg 文件：
#define our ports
#telnet_port 4444
#gdb_port 3333
#commands specific to the Olimex ARM-USB-OCD
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG A"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15BA 0x0003
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1756
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}
if { [info exists ENDIAN ] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
debug_level 3
jtag_khz 100
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#reset_config srst_only
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
#target cortex_m3 little 0 armv7
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
#
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
$_TARGETNAME configure -work-area-backup 0
#working_area 0 0x10000000 0x8000 nobackup
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc1700 $_CCLK calc_checksum
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
#armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
mwb 0xE01FC040 0x01
mwb 0x400FC040 0x01
mwb 0xE000ED08 0x00
}
gdb_flash_program enable
init
#fast enable
jtag_khz 100
debug_level 1
在 Eclipse 中，我使用以下标志调用此工具：
-f arm-usb-ocd.cfg -f debug.cfg
这似乎工作正常（至少我似乎没有在控制台中收到任何错误）。现在是我遇到问题的部分：
我在 GDB 硬件调试下的 Eclipse（运行 > 调试配置...）中创建了一个调试配置。相关参数为：
Main:
C/C++ Application: output\project_UT1.elf
Debugger:
C:\CodeSourcery\bin\arm-none-eabi-gdb.exe
Startup:
Reset and Delay checked (2-seconds)
Halt checked
Initialization commands:
target remote localhost:3333
monitor flash device = LPC1756
monitor flash download = 1
monitor flash breakpoints = 1
monitor endian little
monitor speed 100
monitor speed auto
monitor reset halt
monitor writeu32 0x400FC040 = 0x00000001
monitor clrbp
Load image: not checked
Load symbols: checked
Runtime options: none of Set program counter, set breakpoint or resume checked
Run commands:
monitor reg sp = 0x10001ffc
monitor reg pc = 0x00001278
continue
Using "Standard GDB Hardware Debugging Launcher"
（注意：我已将 pc 设置为 0x00001278，因为那是我的 Reset_Handler 的地址；我知道它应该是 0x00000004 但我正在试验；当它是 0x00000004 时，我遇到了同样的问题......）
当我尝试使用此设置进行调试时，我收到一条消息“GDB 硬件调试暂停”，PC 似乎位于引导加载程序 0x1FFF0080 并且我的调试器似乎不再连接。在控制台中，我看到如下内容：
.
.
.
target remote localhost:3333
0x1fff0080 in ?? ()
.
.
.
continue
Program received signal SIGINT, Interrupt.
0x1fff0080 in ?? ()
例如，在反汇编窗口中，我可以搜索并找到诸如“main”或“Reset_Handler”之类的东西，但反汇编全是“movs r0, r0”——基本上都是零。我不能单步执行（显然，挂起......）即使在 0x1fff0080 它显示“movs r0，r0”。我似乎能够读取 CPU 寄存器（例如，sp 显示 0x10001ffc 和 pc 显示 0x1fff0081 所以也许JTAG接口没有死……）
我闪现的图像应该在 0x00000000（即那里的向量表）。当我执行 dump_image 时，似乎设备已编程并且向量表条目看起来正确。代码保护？如果是这样，我怎样才能做一个明显成功的“转储+图像”？
但是，即使在未连接 JTAG 的情况下插入设备也会导致无法操作。我已经看到与 LPC1768 类似的帖子，但没有找到任何适合我的帖子。非常感谢任何意见或建议。