在调试了我的代码之后，我已经到了编译器接受它的地步，但是它抛出了一个模拟器异常。
我遇到的主要问题是初始化临时数组并在最后添加向量。
用于添加的方法是我在参考中找到的一种，因为您无法添加 STD_LOGIC_VECTORs
谢谢，布兹基
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity signedmult is
port (cand, lier: in std_logic_vector (4 downto 0);
pro: out std_logic_vector (9 downto 0));
end signedmult;
architecture synth of signedmult is
--temp arrays
signal a,b,c,d,e: std_logic_vector(9 downto 0);
begin
process (a,b,c,d,e)
variable j:integer;
begin
for j in 0 to 9 loop
a(j) <= '0';
b(j) <= '0';
c(j) <= '0';
d(j) <= '0';
e(j) <= '0';
end loop;
end process;
process (cand, lier,a,b,c,d,e)
variable i:integer;
begin
for i in 0 to 4 loop
a(i) <= cand(0) and lier(i);
b(i+1) <= cand(1) and lier(i);
c(i+2) <= cand(2) and lier(i);
d(i+3) <= cand(3) and lier(i);
e(i+4) <= cand(4) and lier(i);
end loop;
end process;
a(5) <= a(4); a(6) <= a(4); a(7) <= a(4); a(8) <= a(4);
b(6) <= b(5); b(7) <= b(5); b(8) <= b(5);
c(7) <= c(6); c(8) <= c(6);
d(8) <= d(7);
pro <= std_logic_vector(unsigned(a) + unsigned(b)); -- + c + d + e;
end synth;