我正在尝试从 Verilog 文件中获取以下信息:
- 模块名称
- 引脚列表
- 引脚信息(pinName 或 busName(和矢量范围)、方向)
例如,在 Verilog 文件下面:
module DMU (
A, B, C,
vdd, Z, Q, QN );
output Z;
input A, B,
C, D;
inout vdd;
output [127:0] Q;
output [18:0] QN; //my comment
endmodule
我已经实现的代码:
range = LBRACK + Word(nums) + COLON + Word(nums) + RBRACK
inputDecl = Group("input" + Optional(range) + Group(OneOrMore(Word(alphanums+","), stopOn=SEMI))).setResultsName("inputPins")
inoutDecl = Group("inout" + Optional(range) + Group(OneOrMore(Word(alphanums+","), stopOn=SEMI))).setResultsName("inoutPins")
outputDecl = Group("output" + Optional(range) + Group(OneOrMore(Word(alphanums+","), stopOn=SEMI))).setResultsName("outputPins")
pinsDecl = ~Keyword("endmodule") + (
inputDecl |
inoutDecl |
outputDecl
)
token_module = Keyword("module") + Word(alphanums).setResultsName("moduleName") + LPAR + \
Group(OneOrMore(Word(alphanums+","), stopOn=RPAR).setResultsName("pinsList")) + SEMI + pinsDecl
我有以下我无法解决的错误:
File "/sw/freetools/python/3.7.2/rh60_64/modules_base/lib/python3.7/site-packages/pyparsing.py", line 2625, in parseImpl
raise ParseException(instring, loc, self.errmsg, self)
pyparsing.ParseException: Expected ";" (at char 52), (line:3, col:22)
谁能帮我 ?