system-verilog - 如何在 systemverilog 中转换为 longint unsigned？

Question

我想将逻辑打包数组转换longint unsigned为 systemverilog，然后我可以使用 DPI-C 将其导出为 C++ unsigned long。我使用的模拟器是 Verilator。检查下面的示例。

logic[31:0] v1;
logic[63:0] v2;

int a = signed'(v1); //cast to signed int
int b = int'(v1); //cast to signed int
int unsigned c = unsigned'(v1); //cast to unsigned int
longint d = longint'(v2); //cast to signed long
//longint unsigned e = longint unsigned'(v2); //This doesn't work. I need to cast to unsigned long.

Answer 1

您需要使用创建一个没有空格的 SystemVerilog 类型typedef。这是一个例子：

// ..
typedef longint unsigned uint64_t;
uint64_t e = uint64_t'(v2);

Answer 2

除非需要符号扩展，否则不需要任何类型的演员表。4-state 和 2-state 类型之间已经存在隐式转换。

你可以写：

longint d = v2;