我用谷歌搜索了错误,但没有发现任何有用的信息。Verilog 代码:
`timescale 1us/1ns
module ShadyModule;
reg [3:0] num1,num2;
reg [4:0] res;
`include "ShadyTask.v"
initial
begin
num1 = 5;
num2 = 10;
$monitor ("num1= %d, num2=%d",num1,num2);
ShadyTask(num1,num2,res);
end
endmodule
该ShadyTask.v
文件包含:
task ShadyTask;
input[3:0] num1,num2;
output[4:0] sum;
begin
sum = num1+num2;
end
endtask