接受的答案是错误的,因为第二个代码示例实际上是一个组合代码并且根本不使用时钟,我们需要实现一个顺序代码。第一个代码示例是同步复位:
//Synchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk)
begin
if(rst) // In order to execute this line, clk and reset both have to be in posedge.
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule
第二个代码示例是异步复位:
//Asynchronous Reset
module test(clk,d,rst,a);
input clk,d,rst;
output reg a;
always @(posedge clk, posedge rst)
begin
if(rst) // In order to execute this line, rst has to be in posedge(clk's value doesn't
// matter here, it can be either posedge or negedge, what's important is rst's value).
a <= 1'b0;
else
a <= 1'b1; // assigned to a constant
end
endmodule