chisel - 如何使用黑盒生成 RTL 代码？

Question

当我想用黑盒将代码凿子转换为verilog时，出现错误。我该如何解决？

[error] /data/workspace/chisel/chisel3-3.1.8/src/main/scala/tap/dti_bypass_register.scala:45:18: overloaded method value execute with alternatives:

import chisel3._
import chisel3.util._
  class dti_bypass_register extends BlackBox with HasBlackBoxResource {
  val io = IO(new Bundle {
    val clk_DR          = Input (Clock())// Bypass register clock
    val TDI             = Input (UInt(1.W))// data in
    val bypass_en       = Input (Bool())// enable signal
    val captureDR       = Input (Bool())// captureDR signal

    val TDO_bypass      = Output (UInt(1.W))// Serial data out
  })
    setResource("/dti_bypass_register.v")

}

object dti_bypass_registerDriver extends App {
  chisel3.Driver.execute(args, () => new dti_bypass_register)
}

Answer 1

Chisel 不接受 BlackBoxes 作为顶级模块。由于 BlackBoxes 只是我们为其发出 Verilog 实例化的接口，因此 Chisel 与它们没有任何关系。