我的代码是为接收 4 位数据而编写的，将它们打包成 32 位，并在触发器为 1 时（在 9 个时钟周期后）将它们发送到 arm 处理器
问题是
数据仅在第一个时钟周期存储在我的最终寄存器 l1 中
我从 ise 收到警告，我的 2 个寄存器 sr1 和 sr2 未连接到我的 too 模块（or1），它们在综合中被省略
如果你们帮助我，我将非常感激。
这是我的代码
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-- Create Date: 18:54:09 12/11/2018
-- Design Name: GPS module
-- Module : final1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
port(clk : in std_logic;
digit : out integer range 0 to 16);
end counter;
architecture counter of counter is
begin
count: process (clk)
variable temp : integer range 0 to 17;
begin
if (clk'event and clk='1') then
temp :=temp+1;
if (temp=17) then temp:=0;
end if;
end if;
digit <= temp;
end process count;
end counter;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity test221 is
Port (clk1, rst : in std_logic ; datain : in STD_LOGIC_VECTOR (3 downto 0);
dataout : out STD_LOGIC_VECTOR (31 downto 0));
end test221;
architecture Behavioral of test221 is
signal x : integer range 0 to 16;
component counter
port(clk : in std_logic;
digit : out integer range 0 to 16);
end component;
begin
digit1 : counter port map(clk=> clk1, digit => x );
sr1: process (clk1,rst)
variable n : integer :=0;
begin
n := 0;
if (rst='1') then
dataout <= "00000000000000000000000000000000";
elsif (clk1'event and clk1='1')then
if (x <8) then
if (n>28) then dataout <= "00000000000000000000000000000000" ; n := 0;
end if;
if (x=0 and n=0) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n:=n+4;
elsif (x=1 and n=4) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n:=n+4;
elsif (x=2 and n=8) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n:=n+4;
elsif (x=3 and n=12) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n:=n+4;
elsif (x=4 and n=16) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n:=n+4;
elsif (x=5 and n=20) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n:=n+4;
elsif (x=6 and n=24) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n:=n+4;
elsif (x=7 and n=28) then
dataout(31-n) <= datain(0);
dataout(31-(n+1)) <= datain(1);
dataout(31-(n+2)) <= datain(2);
dataout(31-(n+3)) <= datain(3);
n := n + 1;
end if;
end if;
end if;
end process sr1;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity test222 is
Port (clk2,rst2: in std_logic; datain : in STD_LOGIC_VECTOR (3 downto 0);
dataout2 : out STD_LOGIC_VECTOR (31 downto 0));
end test222;
architecture Behavioral of test222 is
signal y : integer range 0 to 16;
component counter
port(clk : in std_logic;
digit : out integer range 0 to 16);
end component;
begin
digit2 : counter port map (clk=>clk12 , digit => y);
sr2: process (clk2 , rst2)
variable m : integer :=0;
begin
m :=0;
if (rst2='1') then
dataout2 <="00000000000000000000000000000000";
elsif (clk2'event and clk2='1')then
if (y<16 and y>7) then
if (m >28) then dataout2 <= "00000000000000000000000000000000" ; m :=0;
end if;
if (y=8 and m=0) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m:= m+4;
elsif (y=9 and m=4) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m:= m+4;
elsif (y=10 and m=8) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m:= m+4;
elsif (y=11 and m=12) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m:= m+4;
elsif (y=12 and m=16) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m:= m+4;
elsif (y=13 and m=20) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m:= m+4;
elsif (y=14 and m=24) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m:= m+4;
elsif (y=15 and m=28) then
dataout2(31-m) <= datain(0);
dataout2(31-(m+1)) <= datain(1);
dataout2(31-(m+2)) <= datain(2);
dataout2(31-(m+3)) <= datain(3);
m := m + 1;
end if;
end if;
end if;
end process sr2;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity or1 is
port (clk3,rst3:std_logic; tempd1 : in std_logic_vector (31 downto 0);
odata1 : out std_logic_vector (31 downto 0);trig :out std_logic);
end or1;
architecture behavioral of or1 is
signal l1 : std_logic vector (32 downto 0);
signal l2 : std_logic vector (32 downto 0);
signal digitm : integer range 0 to 16 ;
component test221
Port (clk1, rst : in std_logic ; datain : in STD_LOGIC_VECTOR (3 downto 0);
dataout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component test222
Port (clk2,rst2: in std_logic; datain : in STD_LOGIC_VECTOR (3 downto 0);
dataout : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component counter
port( clk : in std_logic;
digit : out integer range 0 to 16);
end component;
begin
digit3 : counter port map (clk=>clk3 , digit => digitm);
sr1 :test221 port map ( dataout => l1);
sr2 : test222 port map (dataout2 => l2);
r : process (clk3,rst3)
begin
If (digitm=8)
Then tirg=‘1’;
Elsif (digitm=16)
Then
trig=‘1’;
Else trig=‘0’;
if (clk3'event and clk3='1' and rst3='0')
then
if (digitm=7)
then
odata1 <= l1;
elsif (digitm=15)
then
odata1 <= l2;
End if;
end if;
end if;
end process r;
end behavioral;