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这是我试图在 Modelsim 中运行的一些 Verilog 代码。
parameter Data_width = 8; //DATA SIZE input CLK, RST; input [Data _width-1:0] D;
当我尝试编译它时,编译器在最后一行抱怨 Data_width ,说它需要一个标识符。我可以对其中的数字进行硬编码以解决问题,但我宁愿使用变量以防万一我想更改它,这样我就不必更改它。如何解决这个问题?
The code you posted has a space between Data and _width in the last line. Change it to:
Data
_width
input [Data_width-1:0] D;