下面的独立 VHDL 文件是从 CLaSH 的输出中简化而来的,这应该可以解释其有些奇怪的结构。
目的是在iss.tup2_sel1(0)
的循环中增加。但是,我在 VHDL 模拟器中看到的是(因此, )在数组更新后变为 unknoqn (其值为)。为什么数组元素会损坏?s.tup2_sel0
"01"
OUTPUT
s.tup2_sel1(0)
"XXXXXXXX"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
entity CHIP8 is
port(-- clock
CLK : in std_logic;
-- asynchronous reset: active high
RESET : in std_logic;
OUTPUT : out unsigned(7 downto 0));
type array_of_unsigned_8 is array (integer range <>) of unsigned(7 downto 0);
type tup2 is record
tup2_sel0 : std_logic_vector(1 downto 0);
tup2_sel1 : array_of_unsigned_8(0 to 1);
end record;
end;
architecture structural of CHIP8 is
signal y1 : array_of_unsigned_8(0 to 1);
signal s : tup2;
signal s1 : tup2;
signal y : array_of_unsigned_8(0 to 1);
signal x : unsigned(7 downto 0);
begin
y <= s.tup2_sel1;
x <= y(0);
process(y)
variable ivec : array_of_unsigned_8(0 to 1);
begin
ivec := y;
ivec(0) := x + 1;
y1 <= ivec;
end process;
with s.tup2_sel0 select
s1 <= (tup2_sel0 => "01", tup2_sel1 => y) when "00",
(tup2_sel0 => "10", tup2_sel1 => y1) when "01",
(tup2_sel0 => "10", tup2_sel1 => y) when others;
process(CLK,RESET)
begin
if RESET = '1' then
s <= (tup2_sel0 => "00", tup2_sel1 => array_of_unsigned_8'(0 to 1 => to_unsigned(0,8)));
elsif rising_edge(CLK) then
s <= s1;
end if;
end process;
OUTPUT <= x;
end;
我的顶级测试平台生成RESET
信号:
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
ENTITY TB IS
END TB;
ARCHITECTURE behavior OF TB IS
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal OUTPUT : unsigned(7 downto 0);
constant CLK_period : time := 10 ns;
BEGIN
uut: entity work.CHIP8 PORT MAP (
CLK => CLK,
RESET => RESET,
OUTPUT => OUTPUT);
CLK_proc :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
RESET_proc: process
begin
RESET <= '1';
wait for CLK_period * 2;
RESET <= '0';
wait;
end process;
END;