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我正在尝试在verilog中实现一个简单的JK触发器FSM。但是我看到输出“q”和“q_not”在多个时间点都是错误的。我在下面展示代码和输出。有人可以让我知道代码有什么问题。特别是我想知道这个实现有什么问题，即使还有其他方法可以实现 JK 触发器。

JK触发器和测试台模块

`timescale 1ns/100ps

module jk_ff(j, k, clk, reset, q, q_not);

input j, k, clk, reset;

output reg q, q_not;

reg present_state, next_state;

parameter state_a = 1'b0;
parameter state_b = 1'b1;

always @ (present_state or j or k)
begin:comb_logic

 next_state = state_a;
 //next_state = 0;

 case(present_state)

  state_a: begin
   if (j == 1'b0 && k == 1'b0) begin
     next_state = state_a;
     end
   else if (j == 1'b0 && k == 1'b1) begin
     next_state = state_a;
     end
   else if (j == 1'b1 && k == 1'b0) begin
     next_state = state_b;
     end
   else if (j == 1'b1 && k == 1'b1) begin
     next_state = state_b;
     end
   end

  state_b: begin
   if (j == 1'b0 && k == 1'b0) begin
     next_state =  state_b;
   end
   else if (j == 1'b0 && k == 1'b1) begin
     next_state = state_a;
   end
   else if (j == 1'b1 && k == 1'b0) begin
     next_state = state_b;
   end
   else if (j == 1'b1 && k == 1'b1) begin
     next_state = state_a;
   end
  end
  default: next_state = state_a;
 endcase 
end

always @ (posedge clk or reset)
begin: seq_logic

if (reset) begin
 q <= 1'b0;
 q_not <= 1'b1;
 present_state <= state_a;
 end
 else begin
 present_state <= next_state;

 case(present_state)

   state_a: begin
    q <= 1'b0;
    q_not <= 1'b1;
   end
   state_b: begin
    q <= 1'b1;
    q_not <= 1'b0;
   end
   default: present_state <= state_a;

  endcase
  end
 end

endmodule

//testbench

module jk_ff_tb;

reg j, k, clk, reset;

wire q, q_not;

jk_ff DUT(.j(j), .k(k), .clk(clk), .reset(reset), .q(q), .q_not(q_not));

initial begin
clk =0;
forever #5 clk = !clk;
end

initial begin
 $monitor("j = %b, k = %b, q = %b, q_not = %b", j, k, q, q_not);
 $dumpfile("jk_ff_wave.vcd");
 $dumpvars;
 reset = 1;
 j=1'b0;
 k=1'b1;
#10 reset = 0;

 #15 j=1'b1;
 #15 k=1'b0;
 #15 j=1'b0;
 #15 k=1'b1;
 #15 j=1'b1;
 #15 k=1'b1;


 #10 $finish;  

end

endmodule

测试台模拟的输出，显示输入值和主要输出值

j = 0, k = 1, reset = 1, q = 0, q_not = 1
j = 0, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 0, reset = 0, q = 1, q_not = 0
j = 1, k = 0, reset = 0, q = 0, q_not = 1
j = 0, k = 0, reset = 0, q = 1, q_not = 0
j = 0, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 1, reset = 0, q = 0, q_not = 1
enter code here

谢谢！

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1 回答 1

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你在这里遇到了各种各样的问题：

  1. 在seq_logic中，您present_state使用阻塞分配进行分配，下一条语句是case(present_state)。这会测试 的旧值present_state，这不是您想要的
  2. 您的 'comb_logic' 进程对 敏感present_state，但您的seq_logic进程会present_state在时钟上升沿发生变化。乍一看，这似乎是正确的做法，但事实并非如此——把它拉出来。你写这个的方式，comb_logic应该只对J和敏感K

这两个足以获得正确的结果，但这对于 JK 来说太复杂了 - 重新开始，将所有内容放在一个时钟进程中，转储下一个逻辑进程，只需使用 JK 的行为 - 加载、设置或切换. 您还应该将当前时间添加到您的$monitor.

于 2018-07-02T08:07:10.507 回答