我正在寻找为某些测试禁用侧面 uvm 组件中的断言的方法。下面的简单代码代表我的环境,并附有需求注释。我以为我可以使用 $assertoff。如果需要额外的仪器来实现这一点,我可以修改 uvm 组件。
import uvm_pkg::*;
`include "uvm_macros.svh"
class tb_env extends uvm_component;
`uvm_component_utils(tb_env)
int exp_val = 0;
int act_val = 0;
function new(string name = "tb_env", uvm_component parent = null);
super.new(name, parent);
endfunction
virtual task run_phase (uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
#10us;
ASRT: assert ( exp_val == act_val) else
`uvm_error(get_name(), "Error");
#10us;
`uvm_info(get_name(), "Done env", UVM_LOW);
phase.drop_objection(this);
endtask : run_phase
endclass
program tb_run;
initial
begin
tb_env env = new("env");
// Requirement: Disable assertion env.ASRT with system call $assertoff(...)
fork
run_test();
begin
#5us;
env.exp_val = 1;
end
join
end
endprogram