module NOR31_1x1(Y,A);
input [31:0] A;
output Y;
wire [29:0] norWire;
nor nor1(norWire[0], A[0], A[1]);
nor nor2(norWire[1], norWire[0], A[2]);
nor nor3(norWire[2], norWire[1], A[3]);
nor nor4(norWire[3], norWire[2], A[4]);
nor nor5(norWire[4], norWire[3], A[5]);
nor nor6(norWire[5], norWire[4], A[6]);
nor nor7(norWire[6], norWire[5], A[7]);
nor nor8(norWire[7], norWire[6], A[8]);
nor nor9(norWire[8], norWire[7], A[9]);
nor nor10(norWire[9], norWire[8], A[10]);
nor nor11(norWire[10], norWire[9], A[11]);
nor nor12(norWire[11], norWire[10], A[12]);
nor nor13(norWire[12], norWire[11], A[13]);
nor nor14(norWire[13], norWire[12], A[14]);
nor nor15(norWire[14], norWire[13], A[15]);
nor nor16(norWire[15], norWire[14], A[16]);
nor nor17(norWire[16], norWire[15], A[17]);
nor nor18(norWire[17], norWire[16], A[18]);
nor nor19(norWire[18], norWire[17], A[19]);
nor nor20(norWire[19], norWire[18], A[20]);
nor nor21(norWire[20], norWire[19], A[21]);
nor nor22(norWire[21], norWire[20], A[22]);
nor nor23(norWire[22], norWire[21], A[23]);
nor nor24(norWire[23], norWire[22], A[24]);
nor nor25(norWire[24], norWire[23], A[25]);
nor nor26(norWire[25], norWire[24], A[26]);
nor nor27(norWire[26], norWire[25], A[27]);
nor nor28(norWire[27], norWire[26], A[28]);
nor nor29(norWire[28], norWire[27], A[29]);
nor nor30(norWire[29], norWire[28], A[30]);
nor result(Y, norWire[29], A[31]);
endmodule
Hi, so I wrote the code above to test if Zero flag is set by nor each bit against another, It seems that the logic is correct, but the result keeps return 1 for zero flag regardless of any input. I ran through the simulation to test and it seems that norWire already contain some value despite not being set any value yet. Can I get some help debugging this please. I'm having a hard time debugging this due to being new to Verilog and the ModelSim simulator.