1

从主要来自 myhdl 示例的代码中：

from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog

__debug = True

def ClkDriver(clk):
    halfPeriod = delay(10)
    @always(halfPeriod)
    def driveClk():
        clk.next = not clk
    return driveClk

def HelloWorld(clk, outs):

    counts = intbv(3)[32:]

    @always(clk.posedge)
    def sayHello():
        outs.next = not outs
        if counts >= 3 - 1:
            counts.next = 0
        else:
            counts.next = counts + 1
        if __debug__:
            print "%s Hello World! outs %s %s" % (
              now(), str(outs), str(outs.next))

    return sayHello

clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)

我希望它生成一个包含initial块的verilog程序，例如：

module HelloWorld(...)
reg [31:0] counts;
initial begin
    counts = 32'h3
end
always @(...

如何获得initial生成的块？

请注意，在 old.myhdl.org/doku.php/dev:initial_values 的谷歌缓存中，它链接到示例https://bitbucket.org/cfelton/examples/src/tip/ramrom/。所以看起来应该支持该功能。但是，rom 示例会生成静态 case 语句。这不是我要找的。

4

1 回答 1

0

解决它的三个步骤：

  • 更新到 master 上的最新 myhdl 或包含87784ad添加问题#105或#150. 作为 virtualenv 的示例，运行 git clone，然后运行pip install -e <path-to-myhdl-dir>​​.
  • 将信号更改为列表。
  • toVerilog.initial_values=True调用前设置toVerilog。

代码片段如下。

def HelloWorld(clk, outs):

    counts = [Signal(intbv(3)[32:])]

    @always(clk.posedge)
    def sayHello():
        outs.next = not outs
        if counts[0] >= 3 - 1:
            counts[0].next = 0
        else:
            counts[0].next = counts[0] + 1
        if __debug__:
            print "%s Hello World! outs %s %s %d" % (
                  now(), str(outs), str(outs.next), counts[0])
    return sayHello

clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
toVerilog.initial_values=True
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)
于 2017-07-05T16:23:05.060 回答