0

我正在做一个需要双向三态缓冲器的项目。我根据我在这个社区和其他一些网站上的搜索开发了一个 VHDL 代码。但它不能正常工作。下面是 VHDL 代码。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Inter_Con_Mod is
    generic(WL: integer := 8);
    port(In1: in signed(WL-1 downto 0);
          RW: in std_logic;
          Data_IO1: inout signed(WL-1 downto 0);
          Out1: out signed(WL-1 downto 0));

end Inter_Con_Mod;

architecture Behav of Inter_Con_Mod is

begin

Data_IO1 <= In1 when RW = '1' else
                (others => 'Z');

Out1 <= Data_IO1;


end Behav;

这是测试台代码：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY InterCon_test IS
END InterCon_test;

ARCHITECTURE behavior OF InterCon_test IS 

     -- Component Declaration for the Unit Under Test (UUT)

     COMPONENT Inter_Con_Mod
     PORT(
            In1 : IN  signed(7 downto 0);


            RW : IN  std_logic;
            Data_IO1 : INOUT  signed(7 downto 0);

            Out1 : OUT  signed(7 downto 0)

          );
     END COMPONENT;


    --Inputs
    signal In1 : signed(7 downto 0) := (others => '0');


    signal RW : std_logic := '0';

    --BiDirs
    signal Data_IO1 : signed(7 downto 0);


    --Outputs
    signal Out1 : signed(7 downto 0);

    -- No clocks detected in port list. Replace <clock> below with 
    -- appropriate port name 

    --constant <clock>_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: Inter_Con_Mod PORT MAP (
             In1 => In1,


             RW => RW,
             Data_IO1 => Data_IO1,

             Out1 => Out1

          );

    -- Clock process definitions
-- Stimulus process
    stim_proc: process
    begin       
        -- hold reset state for 100 ns.
        wait for 5 ns;  
        In1 <= "01111111";
        wait for 5 ns;
        RW <= '1';
        wait for 5 ns;

        RW <= '0';
        wait for 20 ns;
        Data_IO1 <= "00101010";



        wait;
    end process;

END;

但是看看模拟结果中发生了什么：

模拟_结果

我不明白为什么它会忽略我在将 RW 设置为 0 之前提供的测试台刺激。

提前致谢。

4

1 回答 1

0

感谢@user1155120，问题解决了。我已将整个代码更改为以下内容。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Inter_Con_Mod is
    generic(WL: integer := 8);
    port(PortL,PortR: inout signed(WL-1 downto 0);
          RW: in std_logic);

end Inter_Con_Mod;

architecture Behav of Inter_Con_Mod is

begin


 PortR <= PortL when RW = '0' else
            (others => 'Z');

 PortL <= PortR when RW = '1' else
            (others => 'Z');

end Behav;

所以我有 2 个输入端口和 1 个选择输入端口。问题不在模块的代码中。它在测试台上。我必须驱动我需要充当输出的输入端口，以免线路上的数据受到干扰。下面是测试台代码：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY Test IS
END Test;

ARCHITECTURE behavior OF Test IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Inter_Con_Mod
    PORT(
         PortL : INOUT  signed(7 downto 0);
         PortR : INOUT  signed(7 downto 0);
         RW : IN  std_logic
        );
    END COMPONENT;


   --Inputs
   signal RW : std_logic := '0';
    --BiDirs
   signal PortL : signed(7 downto 0);
   signal PortR : signed(7 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 



BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Inter_Con_Mod PORT MAP (
          PortL => PortL,
          PortR => PortR,
          RW => RW
        );




   -- Stimulus process
   stim_proc: process
   begin        

            PortL <= "01111111";
            PortR <= (others => 'Z');

            wait for 5 ns;
            RW <= '1';
            wait for 5 ns;
            PortR <= "01111100";
            PortL <= (others => 'Z');

            wait for 20 ns;



            wait;


      wait;
   end process;

END;

我希望这可以帮助那些像我一样刚接触硬件的人。

于 2017-04-23T03:06:40.780 回答