verilog - Verilog: assign a weighted sum of parameterized length

Question

I am trying to implement a linear feedback shift register with parameterized width and coefficients:

// ...
    parameter width = 16;
    parameter [width-1:0] coeff = 16'b1110101100110110;
// ...

Is there a way to assign the XOR-chain to the input flipflop, i.e. what is a sensible way of implementing something like

assign input_wire = (coeff[0] & flops[0]) xor ... xor (coeff[width-1] & flops[width-1]);

The obvious but illegal way would be using a for-loop. Is there a way to do this outside an always-block?

Thanks

Answer 1

Bitwise AND and the unary XOR-operator do the trick:

assign input_wire = ^(coefficients[width-1:0] & flops[width-1:0]);

The bitwise AND does the weighting of the flipflop outputs.