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我正在尝试编写一个 VHDL 模块，但我遇到了一些输入问题，这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;


entity binary_add is
    port( n1 : in std_logic_vector(3 downto 0);
    n2 : in std_logic_vector(3 downto 0);
    segments : out std_logic_vector(7 downto 0);
    DNout : out std_logic_vector(3 downto 0));

end binary_add;

architecture Behavioral of binary_add is
begin

DNout <= "1110";

process(n1, n2)

variable x: integer;


begin

x:= conv_integer(n1(3)&n1(2)&n1(1)&n1(0)) + conv_integer(n2(3)&n2(2)&n2(1)&n2(0));

if(x = "0") then

segments <= "10000001";

elsif(x = "1") then

segments <= "11001111";

else

segments <= "00000000";

end if;

end process;

end Behavioral;

我收到这些错误：

WARNING:PhysDesignRules:367 - The signal <n1<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n1<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n1<3>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n2<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n2<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <n2<3>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:Par:288 - The signal n1<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n1<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n1<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n2<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n2<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal n2<3>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

这些错误看起来很复杂，但实际上它说，我认为，无法路由我的 n1 和 n2 信号的其他 3 个输入。我不知道为什么会发生这种情况，但我想做的就是将 n1 和 n2 有符号数字的总和显示为 7 段显示。如果有人可以帮助我解决这个问题，我将不胜感激。

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1 回答 1

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第一：不要使用std_logic_arithor std_logic_signed- 我写过为什么不使用. 其次：您创建了一个异步进程，这在设计用于以同步方式使用（以及您希望使用的工具）的 FPGA 中不是很好的做法。创建一个时钟输入并使用它。您可以异步执行此操作，但在您真正知道自己在做什么之前，请避免使用它。一旦你真正知道你在做什么，你很可能也会避免它，因为你明白它会有多糟糕:)

我会让我的端口signed类型和use ieee.numeric_stdd.all;. 甚至使用integer输入端口上的类型。如果这是顶级块，您需要放置一个包装器以将 std_logic_vectors 放在最外面的引脚上，将它们转换为整数并将它们输入您上面编写的块中：

n1 <= to_integer(signed(n1_pins));

然后你需要做这样的事情......

architecture Behavioral of binary_add is
begin
DNout <= "1110";
process(clk)
  variable x: integer;
begin
  x:= n1+n2;
  case x
    when 0 => segments <= "10000001";
    when 1 => segments <= "11001111";

ETC

或创建一个常量数组将整数转换为 7 段并执行

segments <= int_to_7seg(x);
于 2010-11-03T13:48:44.827 回答