我收到了这个问题作为面试前的问题“为满足以下要求的模块绘制图表并编写 VHDL 代码:a. 完全同步。b. 在 11 条总线之间多路复用,其中每条总线为 8 位宽。c. 有2 个延迟周期。d. 针对最大时钟频率进行了优化。”
我一直在尝试自己阅读我在大学完成的旧笔记和作业,但我只是不认为我在正确的轨道上。到目前为止,我已经将代码发布在下面:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux is
port(
A: in STD_LOGIC_vector(7 downto 0);
B: in STD_LOGIC_vector(7 downto 0);
C: in STD_LOGIC_vector(7 downto 0);
D: in STD_LOGIC_vector(7 downto 0);
E: in STD_LOGIC_vector(7 downto 0);
F: in STD_LOGIC_vector(7 downto 0);
G: in STD_LOGIC_vector(7 downto 0);
H: in STD_LOGIC_vector(7 downto 0);
I: in STD_LOGIC_vector(7 downto 0);
J: in STD_LOGIC_vector(7 downto 0);
K: in STD_LOGIC_vector(7 downto 0);
S0: in std_LOGIC_vector(3 downto 0);
Z: out STD_LOGIC_vector(7 downto 0)
);
end Mux;
architecture func of Mux is
begin
process (A,B,C,D,E,F,G,H,I,J,K,S0)
begin
if S0="0001" then
Z<= A;
elsif S0="0010" then
Z<= B;
elsif S0="0011" then
Z<= C;
elsif S0="0100" then
Z<= D;
elsif S0="0101" then
Z<= E;
elsif S0="0110" then
Z<= F;
elsif S0="0111" then
Z<= G;
elsif S0="1000" then
Z<= H;
elsif S0="1001" then
Z<= I;
elsif S0="1010" then
Z<= J;
elsif S0="1011" then
Z<= K;
else
Z<=A;
end if;
end process;
end func;
这是我的第二个文件的代码:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
entity mux11test is
end entity mux11test;
architecture test of mux11test is
signal T_A: STD_LOGIC_vector(7 downto 0):="00000001";
signal T_B: STD_LOGIC_vector(7 downto 0):="00000010";
signal T_C: STD_LOGIC_vector(7 downto 0):="00000011";
signal T_D: STD_LOGIC_vector(7 downto 0):="00000100";
signal T_E: STD_LOGIC_vector(7 downto 0):="00000101";
signal T_F: STD_LOGIC_vector(7 downto 0):="00000110";
signal T_G: STD_LOGIC_vector(7 downto 0):="00000111";
signal T_H: STD_LOGIC_vector(7 downto 0):="00001000";
signal T_I: STD_LOGIC_vector(7 downto 0):="00001001";
signal T_J: STD_LOGIC_vector(7 downto 0):="00001010";
signal T_K: STD_LOGIC_vector(7 downto 0):="00001011";
signal T_S: STD_LOGIC_vector( 3 downto 0);
signal T_Z: STD_LOGIC_vector(7 downto 0);
component mux11 IS
port(
A: in STD_LOGIC_vector(7 downto 0);
B: in STD_LOGIC_vector(7 downto 0);
C: in STD_LOGIC_vector(7 downto 0);
D: in STD_LOGIC_vector(7 downto 0);
E: in STD_LOGIC_vector(7 downto 0);
F: in STD_LOGIC_vector(7 downto 0);
G: in STD_LOGIC_vector(7 downto 0);
H: in STD_LOGIC_vector(7 downto 0);
I: in STD_LOGIC_vector(7 downto 0);
J: in STD_LOGIC_vector(7 downto 0);
K: in STD_LOGIC_vector(7 downto 0);
S0: in std_LOGIC_vector(3 downto 0);
Z: out STD_LOGIC_vector(7 downto 0)
);
END COMPONENT ;
signal clk : std_LOGIC;
constant clk_period: time:=100ns;
begin
umux: Mux11 port map(T_A,T_B,T_C,T_D,T_E,T_F,T_G,T_H,T_I,T_J,T_K,T_S,T_Z);
clk_process:process
begin
clk<='0';
wait for clk_period/2;
clk <='1';
wait for clk_period/2;
end process;
PROCESS
begin
if T_S="0001" then
T_Z <= T_A ;
elsif T_S="0010" then
T_Z <= T_B ; wait for 100 ns;
elsif T_S="0011" then
T_Z <= T_C ; wait for 100 ns;
elsif T_S="0100" then
T_Z <= T_D ; wait for 100 ns;
elsif T_S="0101" then
T_Z <=T_E ; wait for 100 ns;
elsif T_S="0110" then
T_Z <= T_F ; wait for 100 ns;
elsif T_S="0111" then
T_Z <= T_G ; wait for 100 ns;
elsif T_S="1000" then
T_Z <= T_H ; wait for 100 ns;
elsif T_S="1001" then
T_Z <= T_I ; wait for 100 ns;
elsif T_S="1010" then
T_Z <= T_J ; wait for 100 ns;
elsif T_S="1011" then
T_Z <= T_K ; wait for 100 ns;
wait;
end if;
end PROCESS;
end architecture test;
有没有人可以告诉我我是否走在正确的道路上,如果这是完全同步的,我将如何开始实施或确定 2 个延迟周期?