compiler-errors - 编译中的 VHDL 错误

Question

我是 VHDL 的新手，我正在尝试创建一个 ALU，但它在编译中有一些错误。这是代码：

library ieee;
use ieee.std_logic_1164.all;
use work.basic_func.all;

entity askhsh1 is
  port
(   a : in std_logic_vector(15 downto 0);
    b : in std_logic_vector(15 downto 0);
    coin : in std_logic;
    coout : out std_logic;
    s : in std_logic_vector(15 downto 0);
    d : in std_logic_vector(15 downto 0);
    result : out std_logic);


end askhsh1;

architecture structure of askhsh1 is 
  signal c : std_logic_vector(1 to 15);
  signal resultAND : std_logic_vector(15 downto 0);
  signal resultOR : std_logic_vector(15 downto 0);
  signal operator : std_logic_vector(0 to 2);
  signal resultXOR : std_logic_vector(15 downto 0);
  signal binvert : std_logic;
  signal ainvert : std_logic;
  component myAND
    port (in1, in2: in std_logic; out1: out std_logic);
  end component;
  component myOR
    port (in1, in2: in std_logic; out1: out std_logic);
  end component;
  component myXOR
    port (in1, in2: in std_logic; out1: out std_logic);
  end component;
  component fullader
    port (cin, x, y : in std_logic; 
            s, cout : out std_logic);
  end component;
begin 
U1 : myAND port map (a, b, resultAND);

T1 : myOR port map (a, b, resultOR);

 stage0 : fulladder port map (cin => coin, x => a(0),  y => b(0), s => s(0), cout => c(1));
 stage1 : fulladder port map (cin => c(1), x => a(1),  y => b(1), s => s(1), cout => c(2));
 stage2 : fulladder port map (cin => c(2), x => a(2),  y => b(2), s => s(2), cout => c(3));
 stage3 : fulladder port map (cin => c(3), x => a(3),  y => b(3), s => s(3), cout => c(4));
 stage4 : fulladder port map (cin => c(4), x => a(4),  y => b(4), s => s(4), cout => c(5));
 stage5 : fulladder port map (cin => c(5), x => a(5),  y => b(5), s => s(5), cout => c(6));
 stage6 : fulladder port map (cin => c(6), x => a(6),  y => b(6), s => s(6), cout => c(7));
 stage7 : fulladder port map (cin => c(7), x => a(7),  y => b(7), s => s(7), cout => c(8));
 stage8 : fulladder port map (cin => c(8), x => a(8),  y => b(8), s => s(8), cout => c(9));
 stage9 : fulladder port map (cin => c(9), x => a(9),  y => b(9), s => s(9), cout => c(10));
 stage10 : fulladder port map (cin => c(10), x => a(10),  y => b(10), s => s(10), cout => c(11));
 stage11 : fulladder port map (cin => c(11), x => a(11),  y => b(11), s => s(11), cout => c(12));
 stage12 : fulladder port map (cin => c(12), x => a(12),  y => b(12), s => s(12), cout => c(13));
 stage13 : fulladder port map (cin => c(13), x => a(13),  y => b(13), s => s(13), cout => c(14));
 stage14 : fulladder port map (cin => c(14), x => a(14),  y => b(14), s => s(14), cout => c(15));
 stage15 : fulladder port map (cin => c(15), x => a(15),  y => b(15), s => s(15), cout => coout);

 stage0 : fulladder port map (cin => '1', x => a(0), y => (not b(0)), s => s(0), cout => c(1));
 stage1 : fulladder port map (cin => c(1), x => a(1), y => (not b(1)), s => s(1), cout => c(2));
 stage2 : fulladder port map (cin => c(2), x => a(2), y => (not b(2)), s => s(2), cout => c(3));
 stage3 : fulladder port map (cin => c(3), x => a(3), y => (not b(3)), s => s(3), cout => c(4));
 stage4 : fulladder port map (cin => c(4), x => a(4), y => (not b(4)), s => s(4), cout => c(5));
 stage5 : fulladder port map (cin => c(5), x => a(5), y => (not b(5)), s => s(5), cout => c(6));
 stage6 : fulladder port map (cin => c(6), x => a(6), y => (not b(6)), s => s(6), cout => c(7));
 stage7 : fulladder port map (cin => c(7), x => a(7), y => (not b(7)), s => s(7), cout => c(8));
 stage8 : fulladder port map (cin => c(8), x => a(8), y => (not b(8)), s => s(8), cout => c(9));
 stage9 : fulladder port map (cin => c(9), x => a(9), y => (not b(9)), s => s(9), cout => c(10));
 stage10 : fulladder port map (cin => c(10), x => a(10), y => (not b(10)), s => s(10), cout => c(11));
 stage11 : fulladder port map (cin => c(11), x => a(11), y => (not b(11)), s => s(11), cout => c(12));
 stage12 : fulladder port map (cin => c(12), x => a(12), y => (not b(12)), s => s(12), cout => c(13));
 stage13 : fulladder port map (cin => c(13), x => a(13), y => (not b(13)), s => s(13), cout => c(14));
 stage14 : fulladder port map (cin => c(14), x => a(14), y => (not b(14)), s => s(14), cout => c(15));
 stage15 : fulladder port map (cin => c(15), x => a(15), y => (not b(15)), s => s(15), cout =>coout);

 stage0 : fulladder port map (cin => '1', x => (not a(0)), y => b(0), s => s(0), cout => c(1));
 stage1 : fulladder port map (cin => c(1), x =>(not a(1)), y => b(1), s => s(1), cout => c(2));
 stage2 : fulladder port map (cin => c(2), x =>(not a(2)), y => b(2), s => s(2), cout => c(3));
 stage3 : fulladder port map (cin => c(3), x =>(not a(3)), y => b(3), s => s(3), cout => c(4));
 stage4 : fulladder port map (cin => c(4), x =>(not a(4)), y => b(4), s => s(4), cout => c(5));
 stage5 : fulladder port map (cin => c(5), x =>(not a(5)), y => b(5), s => s(5), cout => c(6));
 stage6 : fulladder port map (cin => c(6), x =>(not a(6)), y => b(6), s => s(6), cout => c(7));
 stage7 : fulladder port map (cin => c(7), x =>(not a(7)), y => b(7), s => s(7), cout => c(8));
 stage8 : fulladder port map (cin => c(8), x =>(not a(8)), y => b(8), s => s(8), cout => c(9));
 stage9 : fulladder port map (cin => c(9), x =>(not a(9)), y => b(9), s => s(9), cout => c(10));
 stage10 : fulladder port map (cin => c(10), x =>(not a(10)), y => b(10), s => s(10), cout => c(11));
 stage11 : fulladder port map (cin => c(11), x =>(not a(11)), y => b(11), s => s(11), cout => c(12));
 stage12 : fulladder port map (cin => c(12), x =>(not a(12)), y => b(12), s => s(12), cout => c(13));
 stage13 : fulladder port map (cin => c(13), x =>(not a(13)), y => b(13), s => s(13), cout => c(14));
 stage14 : fulladder port map (cin => c(14), x =>(not a(14)), y => b(14), s => s(14), cout => c(15));
 stage15 : fulladder port map (cin => c(15), x =>(not a(15)), y => b(15), s => s(15), cout => coout);

 P1 : myXOR port map (a, b, resultXOR);

 case (operator) is
    when 0 => output <= resultAND;
    when 1 => output <= resultOR;
    when 2 => 
        if binvert = '0' and ainvert = '0' then
            output <= s;
        elsif binvert = '1' and ainvert = '0' then
            output <= s;
        elsif ainvert = '1' and binvert = '0' then
            output <= s;
        end if;
 end case;



end structure;

错误如下：

错误 (10500)：askhsh1.vhd(97) 靠近文本“case”的 VHDL 语法错误；期待“end”，或“(”，或标识符（“case”是保留关键字），或并发语句。
错误 (10500)：askhsh1.vhd(97) 附近文本“is”处的 VHDL 语法错误；期待“<=”
错误 (10500)：askhsh1.vhd(99) 附近文本“when”处的 VHDL 语法错误；期待“end”，或“(”，或标识符（“when”是保留关键字），或并发语句
错误 (10500)：askhsh1.vhd(100) 附近文本“when”处的 VHDL 语法错误；期待“end”，或“(”，或标识符（“when”是保留关键字），或并发语句
错误 (10500)：askhsh1.vhd(103) 附近文本“elsif”处的 VHDL 语法错误；期待“end”，或“(”，或标识符（“elsif”是保留关键字），或并发语句
错误 (10500)：askhsh1.vhd(105) 附近文本“elsif”处的 VHDL 语法错误；期待“end”，或“(”，或标识符（“elsif”是保留关键字），或并发语句
错误 (10500)：askhsh1.vhd(107) 附近文本“if”处的 VHDL 语法错误；期待“;”或标识符（“if”是保留关键字）或“架构”
信息 (12021): 在源文件 askhsh1.vhd 中找到 0 个设计单元，包括 0 个实体
Info (12021): 在源文件 basic_func.vhd 中找到 9 个设计单元，包括 4 个实体 Info (12022): 找到设计单元 1: basic_func Info (12022): 找到设计单元 2: myAND-modeland Info (12022): 找到design unit 3: myOR-modelor Info (12022): Found design unit 4: myXOR-modelxor Info (12022): Found design unit 5: fulladder-modelfulla Info (12023): Found entity 1: myAND Info (12023): Found entity 2：myOR 信息（12023）：找到实体 3：myXOR 信息（12023）：找到实体 4：fulladder
错误 (293001)：Quartus II 完整编译不成功。9 个错误，1 个警告

compiler-errors - 编译中的 VHDL 错误

0 回答 0

Related

Reference