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我在 vhdl 中做了一个移位寄存器的结构设计。当 WriteShift 为 1 时，我得到移位，当它为 0 时，移位寄存器加载价格。虽然当我在测试台中将 writeshift 设置为 1 时负载工作得很好，但我在模拟中得到了 00000。

我的代码如下：

entity ShiftRegis is
    Port ( Din : in  STD_LOGIC_VECTOR (4 downto 0);
           WriteShift : in  STD_LOGIC;
           Clock : in  STD_LOGIC;
              reset : in  STD_LOGIC;
              En : in STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (4 downto 0));
end ShiftRegis;

architecture Behavioral of ShiftRegis is

component notGate 
    Port ( in0 : in  STD_LOGIC;
           out0 : out  STD_LOGIC);
end component;

component nand4Gate 
    Port ( i0 : in  STD_LOGIC;
           i1 : in  STD_LOGIC;
           i2 : in  STD_LOGIC;
           i3 : in  STD_LOGIC;
           bitOut : out  STD_LOGIC);
end component;

component D_FlipFlop 
    Port ( Din : in  STD_LOGIC;
           En : in  STD_LOGIC;
           Q : out  STD_LOGIC;
              reset : in STD_LOGIC;
           Clk : in  STD_LOGIC);
end component;

signal q4, q3, q2, q1, in3, in2, in1, in0, notWS : std_logic;

begin

ff4 : D_FlipFlop
    port map( Din => Din(4),
             En => En,
             Q => q4,
                reset => reset,
             Clk => Clock);

ff3 : D_FlipFlop
    port map( Din => in3,
             En => En,
             Q => q3,
                reset => reset,
             Clk => Clock);

ff2 : D_FlipFlop
    port map( Din => in2,
             En => En,
             Q => q2,
                reset => reset,
             Clk => Clock);

ff1 : D_FlipFlop
    port map( Din => in1,
             En => En,
             Q => q1,
                reset => reset,
             Clk => Clock);

ff0 : D_FlipFlop
    port map( Din => in0,
             En => En,
             Q => Q(0),
                reset => reset,
             Clk => Clock);

notg4 : notGate
    port map( in0 => WriteShift,
                 out0 => notWS);

nandg3 : nand4Gate
    port map( i0 => Din(3),
             i1 => notWS,
             i2 => WriteShift,
             i3 => q4,
             bitOut => in3);

nandg2 : nand4Gate
    port map( i0 => Din(2),
             i1 => notWS,
             i2 => WriteShift,
             i3 => q3,
             bitOut => in2);

nandg1 : nand4Gate
    port map( i0 => Din(1),
             i1 => notWS,
             i2 => WriteShift,
             i3 => q2,
             bitOut => in1);

nandg0 : nand4Gate
    port map( i0 => Din(0),
             i1 => notWS,
             i2 => WriteShift,
             i3 => q1,
             bitOut => in0);

Q(4) <= q4;
Q(3) <= q3;
Q(2) <= q2;
Q(1) <= q1;

end Behavioral;
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1 回答 1

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您的负载（WriteShift = '1' 和 en = '1'）也不起作用。

有一个设计缺陷，您使用 4 个输入 NAND 门，您需要一个 2:1 多路复用器来选择移位寄存器中四个 LSB 的位Din。q

这是通过使用三个 2 输入 NOR 门创建 2:1 多路复用器来解决的：

architecture behavioral of shiftregis is

    component notgate 
        port ( 
            in0:    in   std_logic;
            out0:   out  std_logic
        );
    end component;

    -- component nand4gate
    --     port (
    --         i0:     in  std_logic;
    --         i1:     in  std_logic;
    --         i2:     in  std_logic;
    --         i3:     in  std_logic;
    --         bitout: out  std_logic
    --     );
    -- end component;

    component nor2gate
        port (
            i0:     in  std_logic;
            i1:     in  std_logic;
            bitout: out  std_logic
        );
    end component;

    component d_flipflop 
        port ( 
            din:    in  std_logic;
            en:     in  std_logic;
            q:      out std_logic;
            reset:  in  std_logic;
            clk:    in  std_logic
        );
    end component;

    signal q4, q3, q2, q1, in3, in2, in1, in0, notws: std_logic;

    signal nor2g0a, nor2g0b: std_logic; -- ADDED
    signal nor2g1a, nor2g1b: std_logic; -- ADDED
    signal nor2g2a, nor2g2b: std_logic; -- ADDED
    signal nor2g3a, nor2g3b: std_logic; -- ADDED
begin

ff4:  
    d_flipflop
        port map (
            din => din(4),
            en => en,
            q => q4,
            reset => reset,
            clk => clock
        );

ff3:  
    d_flipflop
        port map (
            din => in3,
            en => en,
            q => q3,
            reset => reset,
            clk => clock
        );

ff2:  
    d_flipflop
        port map (
            din => in2,
            en => en,
            q => q2,
            reset => reset,
            clk => clock
        );

ff1:  
    d_flipflop
        port map (
            din => in1,
            en => en,
            q => q1,
            reset => reset,
            clk => clock
        );

ff0:  
    d_flipflop
        port map (
            din => in0,
            en => en,
            q => q(0),
            reset => reset,
            clk => clock
        );

notg4:  
    notgate
        port map (
            in0 => writeshift,
            out0 => notws
        );

-- norg3:
--     nand4gate
--         port map (
--             i0 => din(3),
--             i1 => notws,
--             i2 => writeshift,
--             i3 => q4,
--             bitout => in3
--         );

norg3a:  
    nor2gate
        port map (
            i0 => din(3),
            i1 => writeshift,
            bitout => nor2g3a
        );
norg3b:  
    nor2gate
        port map (
            i0 => notws,
            i1 => q4,
            bitout => nor2g3b
        );

nor3gc:  
    nor2gate
        port map (
            i0 => nor2g3a,
            i1 => nor2g3b,
            bitout => in3
        );

-- norg2:
--     nand4gate
--         port map (
--             i0 => din(2),
--             i1 => notws,
--             i2 => writeshift,
--             i3 => q3,
--             bitout => in2
--         );

norg2a:  
    nor2gate
        port map (
            i0 => din(2),
            i1 => writeshift,
            bitout => nor2g2a
        );
norg2b:  
    nor2gate
        port map (
            i0 => notws,
            i1 => q3,
            bitout => nor2g2b
        );

nor2gc:  
    nor2gate
        port map (
            i0 => nor2g2a,
            i1 => nor2g2b,
            bitout => in2
        );


-- norg1:
--     nand4gate
--         port map (
--             i0 => din(1),
--             i1 => notws,
--             i2 => writeshift,
--             i3 => q2,
--             bitout => in1
--         );

norg1a:  
    nor2gate
        port map (
            i0 => din(1),
            i1 => writeshift,
            bitout => nor2g1a
        );
norg1b:  
    nor2gate
        port map (
            i0 => notws,
            i1 => q2,
            bitout => nor2g1b
        );

nor1gc:  
    nor2gate
        port map (
            i0 => nor2g1a,
            i1 => nor2g1b,
            bitout => in1
        );

-- norg0:
--     nand4gate
--         port map (
--             i0 => din(0),
--             i1 => notws,
--             i2 => writeshift,
--             i3 => q1,
--             bitout => in0
--         );

norg0a:  
    nor2gate
        port map (
            i0 => din(0),
            i1 => writeshift,
            bitout => nor2g0a
        );
norg0b:  
    nor2gate
        port map (
            i0 => notws,
            i1 => q1,
            bitout => nor2g0b
        );

nor0gc:  
    nor2gate
        port map (
            i0 => nor2g0a,
            i1 => nor2g0b,
            bitout => in0
        );

    q(4) <= q4;
    q(3) <= q3;
    q(2) <= q2;
    q(1) <= q1;

end architecture behavioral;

这给出了：

shifregis_tb_fixed.png

您在 q(0) 上看到 A 和 B 之间输出“0”，B 和 C 输出“1”，C 和 D 输出“0”，D 和 E 输出“1”，E 和 F 输出“1” ，然后移入 Din(4) 的值，因为 ff4 的 din 输入上没有多路复用器。

您会注意到 LSB 首先熄灭。

重复实例化的组件通常可以成为使用生成语句的目标。

如果没有最小、完整和可验证的示例，我不得不猜测并确定 D_flipflop 组件的异步复位。

于 2016-05-07T10:11:12.327 回答