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您好正在尝试为使用 JK 触发器的 D 触发器以及使用 SR 触发器的 JK 触发器编写结构和测试台代码。但我遇到了一些错误。请任何人都可以帮助我提前谢谢。这是我的编码

  1. D2jk 的结构

     `timescale in/1ps
 module d2jkflip(j,k,clk,q,qbar);
    wire D;

    assign D=(j&~q)|(~k&q);

    dff DFF0(q,qbar,D,clk);

 endmodule

D2jk 的测试台代码

    `timescale in/1ps

    module test_d2jkflip(j,k,clk,q,qbar);
       input j,k,clk;

       wire  D;

       reg   q;

       assign qbar=~q;

       always @(posedge clk)
         if({j,k}==2'b00) 
           q<=q;
         else
           if({j,k}==2'b01) 
             q<=1'b0;
           else
             if({j,k}==2'b10) 
               q<=1'b1;
             else
               if({j,k}==2'b11) 
                 q<=~q;
               else
                 q<=1'bx;
    endmodule

得到这样的错误

Error-[PNDIID] Port not defined in IO declaration
 d2jk.v, 2
   Identifier 'k' is not defined in IO declaration
  Source info: : k
  Please refer to LRM [1364-2001], section 12.3.3.

Error-[PNDIID] Port not defined in IO declaration

d2jk.v, 2
  Identifier 'clk' is not defined in IO declaration
  Source info: : clk
  Please refer to LRM [1364-2001], section 12.3.3.

Error-[PNDIID] Port not defined in IO declaration

d2jk.v, 2
  Identifier 'Qbar' is not defined in IO declaration
  Source info: : Qbar
  Please refer to LRM [1364-2001], section 12.3.3.

Error-[PNDIID] Port not defined in IO declaration

d2jk.v, 2
  Identifier 'Q' is not defined in IO declaration
  Source info: : Q
  Please refer to LRM [1364-2001], section 12.3.3.

Parsing design file 'test_d2jk.v'
Error-[SE] Syntax error
  Following verilog source has syntax error :
  "test_d2jk.v", 8: token is '<'
  if({j,k}==2'b00) Q< =Q
                     ^
6 errors

  1. jk2sr的结构代码

    `timescale 1ns/1ps

module jk2sr(j,k,Clk,r,s,Q,Qbar);
   input j,k;
   input Clk;
   input r;
   input s;
   input Q;
   output Qbar;
   reg    Qbar;

   always@ (posedge(Clk))
     begin
        if(r == 1) 
          Qbar = 0;
        else if(s == 1)
          Qbar = 1; 
        else
          if(Q == 1) 
            if(J == 0 && K == 0)
              Qbar = Qbar; 
            else if(J == 0 && K == 1)
              Qbar = 0; 
            else if(J == 1 && K == 0)
              Qbar = 1;
            else 
              Qbar = ~Qbar;
            else 
              Qbar = Qbar;
     end 
endmodule

JK2SR 的测试台代码

    `timescale 1ns/1ps

    module test_jk2sr(s,r,clk,Q,Qbar);
       input s,r,clk;
       output Q,Qbar;
       reg [1:0] sr;

       always @(posedge clk)
         begin
            sr={s,r}
               begin
                  case(sr)
                    2'd1:Q=1'b0; 
                    2'd2:Q=1'b1;
                    2'd3:Q=1'b1;
                  end       
         endcase  
               end     
    else begin
       Q=1'b0;      
    end   
            Qbar=~Q;
         end 

    endmodule
4

2 回答 2

1

好吧，看起来大多数错误来自未定义输入和输出。你需要指定这个，否则它会给你错误。我的建议是选择一种编码风格，使定义这些更明显，例如：

module jk2sr (
   input wire j,
   input wire k,
   input wire Clk,
   input wire r,
   input wire s,
   input wire Q,
   output reg Qbar
);

// ...

endmodule

我也建议重写

     if({j,k}==2'b00) 
       q<=q;
     else
       if({j,k}==2'b01) 
         q<=1'b0;
       else
         if({j,k}==2'b10) 
           q<=1'b1;
         else
           if({j,k}==2'b11) 
             q<=~q;
           else
             q<=1'bx;

有这样的案例陈述：

case ({j,k})
    2'b00: q <= q;
    2'b01: q <= 1'b0;
    2'b10: q <= 1'b1;
    2'b11: q <= ~q;
    default: q <= 1'bx;
endcase
于 2015-11-24T08:19:05.393 回答
0

应声明所有 IO 方向。亚历克斯发布了一种类型。这是另一种类型。

module d2jkflip(
  j,k,clk,r,s,q,qbar
);
input j,k,clk,r,s,q;    //If you don't declare whether these signals are
                          "wire" or "reg". Their default type is "wire"
output reg qbar;
//output qbar;    reg qbar;    //This is also legal

// ...

endmodule

并且在测试台文件中，一般来说，来自您的设计的输入必须是reg，而设计的输出必须是wire（一些例外，如output wire设计等）。

于 2015-11-25T15:13:11.970 回答