vhdl - 4位幅度比较器VHDL

Question

我必须在 VHDL 中制作一个 4 位幅度比较器，只有并发语句（没有 if/else 或 case/when）。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Exercise is
port (  A : in std_logic_vector (3 downto 0);
        B : in std_logic_vector (3 downto 0);
        Ag : out std_logic;
        Bg : out std_logic;
        AeqB: out std_logic
       );   
end Exercise;

architecture Comparator of Exercise is

begin
    Ag <= '1'when (A>B) else '0'; 
    Bg <= '1' when (B>A) else '0';  --Problem: Here if i sumulate B="ZZZZ", Bg is 1, asi if B>A 
    AeqB<= '1' when (A=B) else '0'; 
end Comparator; 

问题是我需要计算std_logic的所有其他值（U，X，Z，W，L，H，-），我知道有others但无法弄清楚如何用with/select语句制作比较器。

谢谢

Answer 1

通常，您可以“转换” std_logic 可以采用0或1使用该to_01函数的各种值。我认为它在包装中numeric_std。

Answer 2

library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity comp_4 is
    port (  A:IN STD_LOGIC_VECTOR(0 to 3);
        B:IN STD_LOGIC_VECTOR(0 to 3);
        ET:OUT STD_LOGIC;
        GT:OUT STD_LOGIC;
        LT:OUT STD_LOGIC);

    end comp_4;

    architecture dataflow of comp_4 is

    begin
    with A-B(0 to 3) select

    ET <=   '1' when "0000",
        '0' when others;

    with A > B select

    GT <=   '1' when true,
        '0' when others;

    with A < B select

    LT <=   '1' when true,
        '0' when others;

    end dataflow;