testing - Vhdl 测试台未知语法错误

Question

我正在尝试编写一个测试台，但 Vivado 告诉我在特定行上有一个语法错误。我无法意识到我做错了什么。任何人都可以帮忙。

这是我的 tb 代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Numeric_Std.all;

entity mmu_tb is
end mmu_tb;

architecture test of mmu_tb is

  component mmu
    port (
      virt : in std_logic_vector(15 downto 0);
      phys : out std_logic_vector(15 downto 0);
      clock   : in  std_logic;
      we      : in  std_logic;
      datain  : in  std_logic_vector(7 downto 0)
    );
  end component;

  signal virt    std_logic_vector(15 downto 0);
  signal phys    std_logic_vector(15 downto 0);
  signal clock   std_logic;
  signal we      std_logic;
  signal datain  std_logic_vector(7 downto 0);

  constant clock_period: time := 10 ns;
  signal stop_the_clock: boolean;

begin

  mmu : mmu port map ( virt   => virt,
                     phys   => phys,
                     clock  => clock,
                     we     => we,
                     datain => datain);

 stimulus : process
     begin
     -- whatever
     end process;

     clocking: process
       begin
         while not stop_the_clock loop
           clock <= '1', '0' after clock_period / 2;
           wait for clock_period ;
         end loop;
         wait;
       end process;


end test;

这是我得到的错误：

[HDL 9-806] “std_logic_vector”附近的语法错误。["C:/ram/ram/ram.srcs/sim_1/new/mmu_tb.vhd":20]

感谢您的时间。

Answer 1

缺少:，所以第 20 行应该是：

signal virt : std_logic_vector(15 downto 0);

和后续行类似。