我正在尝试编写一些代码来模拟具有两个三态缓冲器和一个 VHDL 中的上拉电阻的电路。下面是我的代码:
library ieee;
use ieee.std_logic_1164.all;
entity PullUpResistor is
port (
A, S, B, T : IN std_logic; -- select one of these four inputs
TriOut : OUT std_logic -- output (no ";" after last port)
);
end entity PullUpResistor;
architecture behavioral of PullUpResistor is
begin
process(A, S, B, T) is
when (S = '1') and (T = '0') => TriOut <= A;
when (S = '0') and (T = '1') => TriOut <= B;
when (S = '0') and (T = '0') => TriOut <= 'H';
when (S = '1') and (T = '1') => TriOut <= 'X';
end process;
end architecture behavioral;
我near "when": syntax error
在第 14 行遇到编译器错误,这是该when (S = '1') and (T = '0') => TriOut <= A;
行。我一生都无法弄清楚语法错误是什么。
任何帮助将不胜感激。
谢谢。