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我正在尝试创建一个用于 NCO 的累加器,但出现了一些奇怪的错误。我对 VHDL 相当陌生,因此感谢您的帮助,这是我的代码:

library IEEE;
use IEEE.STD_LOGIC_1164.all;    -- for std_logic and std_logic_vector
use IEEE.NUMERIC_STD.all;       -- for unsigned type

---------------------------------------------------------------------
-- accumulator entity declaration
---------------------------------------------------------------------       

entity accumulator is

    port(CLK, Reset : in std_logic;
         S  : in std_logic_vector(11 downto 0);
           N : out std_logic_vector(7 downto 0));
end accumulator;

---------------------------------------------------------------------
-- accumulator architecture                                        
---------------------------------------------------------------------   

architecture accumulator_arch of accumulator is

begin   

process (CLK)
      variable ACC : unsigned(11 downto 0) := "000000000000";
      variable STEP : unsigned(11 downto 0) := "000000000000";
    begin
        -- use an "if" statement to synchronise to rising clock edge
        STEP := unsigned(S);
        if (Reset = '1') then
          ACC := "000000000000";

        elsif   rising_edge(clk) then

            ACC := ACC + S;
            --add step size to ACC
        end if;

        N <= std_logic_vector(ACC(11 downto 4));

end process;

end accumulator_arch;

我得到的错误是:

** Error: C:/Modeltech_pe_edu_10.4/Projects/NCO.vhd(34): No feasible entries for infix operator "+".
** Error: C:/Modeltech_pe_edu_10.4/Projects/NCO.vhd(34): Bad right hand side (infix expression) in variable assignment.
** Error: C:/Modeltech_pe_edu_10.4/Projects/NCO.vhd(42): VHDL Compiler exiting

我不明白为什么会出错,因为我要添加两个无符号变量。

谢谢

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1 回答 1

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您正在将 ACC(无符号)与 S(std_logic_vector)相加。您可能打算改用 STEP(无符号)。

此外,由于您使用了异步重置,因此您必须将重置添加到过程敏感度列表中,否则模拟将与实现不匹配。

我认为在这种情况下您会想要同步重置,因为我希望重置由顶级模块而不是全局重置驱动。您可以通过将其移动到rising_edge 块内来使重置同步:

if rising_edge(clk) then
    if (Reset = '1') then
        ACC := (others => '0');
    else
        ACC := ACC + STEP;
    end if;
end if;
于 2015-03-04T12:52:34.487 回答