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我对 VHDL ALU 代码有疑问。我必须用 4 位操作数做 4 个操作的简单 ALU。我正确地实现了这些操作并且它们运行良好。为了执行，我使用 E2LP 板。为了选择操作，我选择了 4 个 JOY 按钮，每个操作一个。问题是，当我按下按钮执行操作并按下它时，我希望结果保持在 LED 上，而我没有选择任何其他操作，但这并没有发生。对于前 5 个 LED，这可以正常工作，但上面的 3 个则不行。这只适用于一个操作。我的模拟结果是正确的。这是项目模式的代码。提前谢谢你。

----------------------------------------------------------------------------------  Control logic
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


    Port ( --clk : in STD_LOGIC;
              in_saberi : in  STD_LOGIC;
           in_mnozi : in  STD_LOGIC;
           in_ili : in  STD_LOGIC;
           in_rotiraj : in  STD_LOGIC;
           out_saberi : out  STD_LOGIC;
           out_mnozi : out  STD_LOGIC;
           out_ili : out  STD_LOGIC;
           out_rotiraj : out  STD_LOGIC);
end upravljanje;

architecture Behavioral of upravljanje is
signal tmps : std_logic := '1';
signal tmpm : std_logic := '1';
signal tmpi : std_logic := '1';
signal tmpr : std_logic := '1';

begin
logika : process(in_saberi,in_mnozi,in_ili,in_rotiraj)
begin
    if (in_saberi='0' and in_mnozi='1' and in_ili='1' and in_rotiraj='1') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_mnozi='0' and in_saberi='1' and in_ili='1' and in_rotiraj='1') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_saberi='1' and in_mnozi='1' and in_ili='0' and in_rotiraj='1') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_saberi='1' and in_mnozi='1' and in_ili='1' and in_rotiraj='0') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_saberi='1' and in_mnozi='1' and in_ili='1' and in_rotiraj='1') then
        tmps <=  tmps;
        tmpm <= tmpm;
        tmpi <= tmpi;
        tmpr <= tmpr;
    else
        tmps <= '1';
        tmpm <= '1';
        tmpi <= '1';
        tmpr <= '1';
    end if;

end process logika;
    out_saberi <= tmps;
    out_mnozi <= tmpm;
    out_ili <= tmpi;
    out_rotiraj <= tmpr;

end Behavioral;


--------------------------------------------------------------------------

-- this is for operation add
entity sabirac is
    Port ( clk : in  STD_LOGIC;
              data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           saberi : in  STD_LOGIC;
           result : out  STD_LOGIC_VECTOR (7 downto 0));
end sabirac;

architecture Behavioral of sabirac is
signal c : std_logic_vector (5 downto 0) := "000000";
signal tmp : std_logic_vector (7 downto 0) := "00000000";

begin
sabiranje : process(clk,saberi)
begin
    if (saberi='0') then
        tmp(0) <= data1(0) xor data2(0);
        c(0) <= data1(0) and data2(0);
        tmp(1) <= data1(1) xor data2(1) xor c(0);
        c(1) <= (data1(1) and data2(1)) or (data1(1) and c(0)) or (data2(1) and c(0));
        tmp(2) <= data1(2) xor data2(2) xor c(1);
        c(2) <= (data1(2) and data2(2)) or (data1(2) and c(1)) or (data2(2) and c(1));
        tmp(3) <= data1(3) xor data2(3) xor c(2);
        if(data1(3) = data2(3)) then
            c(3) <= (data1(3) and data2(3)) or (data1(3) and c(2)) or (data2(3) and c(2));
            tmp(4) <= c(3);
            tmp(5) <= c(3);
            tmp(6) <= c(3);
            tmp(7) <= c(3);
        else
           c(3) <= data1(3) xor data2(3) xor c(2);
            tmp(4) <= c(3);
            tmp(5) <= c(3);
            tmp(6) <= c(3);
            tmp(7) <= c(3);
        end if;


    else
        tmp <= "ZZZZZZZZ";
    end if;
end process sabiranje;

    result <= tmp;

end Behavioral;

-----------------------------------------------------------------------------

entity mul is
    Port (
              clk : in STD_LOGIC;
              pomnozi : in STD_LOGIC;
              data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           result : out  STD_LOGIC_VECTOR (7 downto 0));
end mul;

architecture Behavioral of mul is

begin
mnozenje : process (clk,pomnozi)
begin
    if (pomnozi='0') then
        result <= std_logic_vector(signed(data1) * signed(data2));
    else
        result <= "ZZZZZZZZ";
    end if;     
end process mnozenje;

end Behavioral;

--------------------------------------------------------------------------

entity rotate is
    Port ( clk : in  STD_LOGIC;
           rotiraj : in  STD_LOGIC;
           data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           result : out  STD_LOGIC_VECTOR (7 downto 0));
end rotate;

architecture Behavioral of rotate is
signal tmp : std_logic_vector (3 downto 0) := "0000";
signal tmp2 : std_logic_vector (7 downto 0) := "00000000";

begin
rotacija : process(clk,rotiraj)
begin
    if (rotiraj='0') then

        tmp <= std_logic_vector(rotate_left(unsigned(data1),to_integer(unsigned(data2))));
        tmp2(0) <= tmp(0);
        tmp2(1) <= tmp(1);
        tmp2(2) <= tmp(2);
        tmp2(3) <= tmp(3);
        tmp2(4) <= '0';
        tmp2(5) <= '0';
        tmp2(6) <= '0';
        tmp2(7) <= '0';
    else
        tmp2 <= "ZZZZZZZZ";
    end if;
end process rotacija;
    result <= tmp2;
end Behavioral;

--------------------------------------------------------------------------
-- Logic OR operation
entity logicko_ILI is
    Port ( clk : in  STD_LOGIC;
           data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           logili : in  STD_LOGIC;
           result : out STD_LOGIC_VECTOR (7 downto 0));
end logicko_ILI;

architecture Behavioral of logicko_ILI is
signal c : std_logic_vector (5 downto 0) := "000000";
signal tmp : std_logic_vector (7 downto 0) := "00000000";

begin
logicko : process(clk,logili)
begin
    if (logili = '0') then
        tmp(0) <= data1(0) or data2(0);
        tmp(1) <= data1(1) or data2(1);
        tmp(2) <= data1(2) or data2(2);
        tmp(3) <= data1(3) or data2(3);
        tmp(4) <= '0';
        tmp(5) <= '1';
        tmp(6) <= '1';
        tmp(7) <= '1';
    else
        tmp <= "ZZZZZZZZ";
    end if;
end process logicko;

  result <= tmp;    

end Behavioral;
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2 回答 2

0

我认为你甚至应该在进程中使用你的 clk 和 reset 信号。你的设计是完全异步的！这是一个非常糟糕的主意。

带有异步重置的同步过程如下所示：

test : process (clk,reset)
begin
if (reset) then
 c = 0;
elsif (rising_edge(clk)) then
 c = a + b;
end if;
end process:
于 2015-02-03T14:19:07.730 回答
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您的敏感度列表都不正确。这不符合关于可合成 RTL 的 IEEE 标准。获得与您的模拟结果不同的综合结果的风险很高。

line: 24    Incomplete sensitivity list. Missing signals: tmpm, tmps, tmpr, tmpi
line: 86    Incomplete sensitivity list. Missing signals: data1, data2, c
line: 137   Incomplete sensitivity list. Missing signals: data1, data2
line: 166   Incomplete sensitivity list. Missing signals: tmp, data1, data2
line: 205   Incomplete sensitivity list. Missing signals: data1, data2,

（行号可能会稍微偏离，因为我必须为 添加 use/library 子句ieee.std_logic_1164）

请检查综合结果是否有警告，或在综合之前使用 VHDL 代码检查器。

于 2015-02-01T19:22:06.823 回答