我是 SystemVerilog 的新手,我想验证生成内存中的值。
generate
genvar g0, j;
for( g0 = 0; g0 < NB_CFGDUMP_SLAVE; g0 = g0 + 1)
begin : g_slave
cfgdump_chiplet slave (
.rst_n (presetn),
.clk (pclk),
.cfg_id (8'(g0)), //CONV_STD_LOGIC_VECTOR(g0, 8)),
.data_in (data_in),
.shift (shift),
.data_out (s_data_cfgdump_to_apb[g0]),
.cfgdump_addr (s_cfgdump_addr[g0]),
.cfg_data (s_cfg_data[g0]),
.cfg_write (s_cfg_write[g0]),
.read_data0 (s_read_data[g0][0][33:0]),
.read_data1 (s_read_data[g0][1][33:0]),
.read_data2 (s_read_data[g0][2][33:0]),
.read_data3 (s_read_data[g0][3][33:0]),
.read_data4 (s_read_data[g0][4][33:0]),
.read_data5 (s_read_data[g0][5][33:0]),
.read_data6 (s_read_data[g0][6][33:0]),
.read_data7 (s_read_data[g0][7][33:0]),
.read_data8 (s_read_data[g0][8][33:0]),
.read_data9 (s_read_data[g0][9][33:0]),
.read_data10 (s_read_data[g0][10][33:0]),
.read_data11 (s_read_data[g0][11][33:0]),
.read_data12 (s_read_data[g0][12][33:0]),
.read_data13 (s_read_data[g0][13][33:0]),
.read_data14 (s_read_data[g0][14][33:0]),
.read_data15 (s_read_data[g0][15][33:0]),
.wr_ready (16'(1)), // ACK write from register
.cfg_sel (s_cfg_sel[g0])
);
for( j = 0; j < nb_target_by_slave; j = j + 1)
begin : g_ram
ram ram_i (
.clk (pclk),
.we (s_cfg_write[g0]),
.sel (s_cfg_sel[g0][j]),
.address (s_cfgdump_addr[g0]),
.datain (s_cfg_data[g0]),
.dataout (s_read_data[g0][j][31:0])
);
//end
// Redirection du ready sur le bit de poid fort du bus de lecture
assign s_read_data[g0][j][33] = s_cfg_sel[g0][j];
// Redirection du code d'erreur sur le bit de poid 32 du bus de lecture
assign s_read_data[g0][j][32] = 1;
我尝试转储每个 RAM 的值但没有成功,或者找到一个解决方案来验证读取的值是否符合预期。有人可以帮助我吗?