-1

我正在尝试调试下面显示的代码。我对 SystemVerilog 还很陌生,希望我能从中学习。让我知道任何建议。

**我收到的错误是:

  Error-[ICPSD] Invalid combination of drivers
  Variable "Q" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  "divide.v", 13: logic [7:0] Q;
  "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
  "divide.v", 23: Q = 8'b0;

  Error-[ICPSD] Invalid combination of drivers
  Variable "R" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  "divide.v", 13: logic [7:0] R;
  "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
  "divide.v", 24: R = y;

**我的 SystemVerilog 代码是:

module divide8bit(
  input logic [7:0] x,y,
  input logic clk,
  output logic [7:0] Q,R);

  always_ff @(posedge clk)
    begin
      R <= R-x;
      Q <= Q + 8'd1;
    end
endmodule

module test1;

  logic [7:0] x,y,Q,R;
  logic clk;

  divide8bit testcase1 (x,y,clk,Q,R);

  initial 
    begin
            x = 8'd2;
            y = 8'd8;
            Q = 8'd0;
            R = y;
            clk = 1'd0;
            while(x <= R)
                begin
                    #5 clk = ~clk;
                end
            #5 $finish; 
        end
endmodule
4

1 回答 1

1

同样的问题:你正在分配到QR内部module test1。同时module testcase1也在努力争取QR。不要分配给 Q 和 R test1

于 2014-09-21T05:15:08.830 回答