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我在运行测试平台以及基于两个现有 D-FF 构建的同步器时遇到了这个错误。

File "/home/runner/design.py", line 28, in Sync
    @always_seq(clk.posedge, reset=reset)
  File "/usr/share/myhdl-0.8/lib/python/myhdl/_always_seq.py", line 76, in _always_seq_decorator
    raise AlwaysSeqError(_error.ArgType)
myhdl.AlwaysError: decorated object should be a classic (non-generator) function

我的测试平台概述如下

from myhdl import *
from random import randrange

HALF_PERIOD = delay(10)   ### This makes a 20-ns clock signal
ACTIVE_HIGH = 1
G_DELAY = delay(15)

def Main():
### Signal declaration
    clk, d, dout = [Signal(intbv(0)) for i in range(3)]
    reset = ResetSignal(1,active=ACTIVE_HIGH,async=True)


### Module Instantiation

    S1 = Sync(dout, d, clk,reset)

### Clk generator

    @always(HALF_PERIOD)
    def ClkGen():
        clk.next = not clk


### TB def
    @instance
    def Driver():
        yield(HALF_PERIOD)
        reset.next = 0
        for i in range(4):
            yield(G_DELAY)
            d.next = not d 
        raise StopSimulation 

    return ClkGen, Driver, S1

m1 = traceSignals(Main)
sim = Simulation(m1)
sim.run()

我的同步器编码如下。

from myhdl import *
from DFF import *

def Sync(dout,din,clk,reset):

    """ The module consists of two FFs with one internal signal

    External signals 

    dout : output
    din  : input
    clk  : input

    Internal signal:

    F2F : output-to-input signal that connects two FFs together

    """
### Connectivity

    F2F = Signal(intbv(0))

    F1 = DFF(F2F,din,clk,reset)  
    F2 = DFF(dout,F2F,clk,reset)

### Function

    @always_seq(clk.posedge,reset=reset)
    def SyncLogic():
        if reset:
            F2F.next = 0
            dout.next = 0
        else:
        F2F.next = din
        yield(WIRE_DELAY)
        dout.next = F2F
    return SyncLogic

FF原型编码如下。

from myhdl import *

def DFF(dout,din,clk,reset):

    @always_seq(clk.posedge, reset=reset)
    def Flogic():
        if reset:
            dout.next = 0
        else:
            dout.next = din
    return Flogic

测试平台确实可以与我之前编写的类似测试平台一起工作（稍作修改），但是当将两个模块组合在一起时它不起作用。请说清楚。谢谢你。

4

1 回答 1

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要对线路延迟建模，请使用 Signal 中的“延迟”参数。

改变

@always_seq(clk.posedge,reset=reset)
def SyncLogic():
    if reset:
        F2F.next = 0
        dout.next = 0
    else:
    F2F.next = din
    yield(WIRE_DELAY)
    dout.next = F2F
return SyncLogic

至：

dout = Signal(<type>, delay=WIRE_DELAY)
# ...
@always_seq(clk.posedge, reset=reset)
def synclogic():
    dout.next = din

使用“always_seq”不要定义重置（它是自动添加的）。如果您想明确定义重置，请使用“@always(clock.posedge, reset.negedge)”。

于 2014-06-20T18:36:33.517 回答