scala - chisel/scala 中的 clk 事件

Question

前段时间我写了一个vhdl代码来描述一个D型触发器。一段代码是：

if (clk'event and clk='1') then
      q <= d;
end if;

如何实现以下条件

clk'event

用scala / chisel语言？

Answer 1

我对你的问题有点困惑——一般来说，在 Chisel 中没有明确的时钟。此外，没有理由编写自己的触发器，因为您只需使用 Chisel 提供的 Reg() 构造。

现在的例外是，如果您正在处理多个时钟域，在这种情况下（无论如何根据用户手册），

val q = Reg(init=UInt(0), clock=myClock)

但除非你真的知道你在用多时钟域硬件设计做什么，否则我不建议这样做。

Answer 2

我认为错误是因为您需要通过初始化寄存器来指定 x 和 y 的默认值： val x = Reg(init = UInt(0)) val y = Reg(init = UInt(0))

但是，我认为这是您实际上想要等效于 VHDL 代码的内容：

  class DFF extends Module {
    val io = new Bundle
    {
      val d  = UInt(INPUT,  1)
      val q = UInt(OUTPUT, 1)
    }
    val out = Reg(UInt(width=1))
    when(Bool(true)) {
      out := io.d
    }
    io.q := out
  }

Answer 3

我想到了这样的事情：

class DFF extends Module { 

  val io = new Bundle { 
  val d  = UInt(INPUT,  1) 
  val ck  = UInt(INPUT, 1) 
  val q  = UInt(OUTPUT, 1) 
  val notq  = UInt(OUTPUT, 1)  
  } 

  val x  = Reg(UInt()) 
  val y  = Reg(UInt()) 

  x := io.q
  y := io.d

  when   (ck) { x := io.q; y:= x } 

}

你怎么看？

Answer 4

显然它不起作用。我修改了DFF.scala中的代码：

import Chisel._  

class DFF extends Module 
{ 

val io = new Bundle 
{ 
  val d  = UInt(INPUT,  1)  
  val en = Bool(INPUT)
  val q  = UInt(OUTPUT, 1) 
  val notq  = UInt(OUTPUT, 1)  
} 

val x  = Reg(UInt()) 
val y  = Reg(UInt()) 

when (io.en) { x := io.d; io.q := y; y := x } 
io.notq := !(io.q)
}

但是当我运行这个命令时：

sbt "run main --backend v"

我收到此错误：

[info] Set current project to dff-project (in build file:/home/francesco/Scrivania/Chisel-Project/CHILA/DFF-project/)
[info] Running TestMain main --backend v
backend elaborate
// COMPILING class DFF(0)
started inference
finished inference (2)
start width checking
finished width checking
started flattening
finished flattening (6)
[warn] NativeMethodAccessorImpl.java:-2: 'main' is an unknown argument. in class sun.reflect.NativeMethodAccessorImpl
[error]: NO DEFAULT SPECIFIED FOR WIRE: /*? in class DFF*/ Chisel.UInt(OUTPUT, width=1, connect to 0 inputs: ()) in component class DFF
Re-running Chisel in debug mode to obtain erroneous line numbers...
backend elaborate
// COMPILING class DFF(0)
started inference
finished inference (2)
start width checking
finished width checking
started flattening
finished flattening (6)
[warn] NativeMethodAccessorImpl.java:-2: 'main' is an unknown argument. in class     sun.reflect.NativeMethodAccessorImpl
[error] DFF.scala:6: NO DEFAULT SPECIFIED FOR WIRE: /*? in class DFF*/ Chisel.UInt(OUTPUT,    width=1, connect to 0 inputs: ()) in component class DFF in class DFF
[error] (run-main-0) java.lang.IllegalStateException: CODE HAS 1 ERRORS and 1 WARNINGS
java.lang.IllegalStateException: CODE HAS 1 ERRORS and 1 WARNINGS
at Chisel.ChiselError$.checkpoint(ChiselError.scala:119)
at Chisel.Backend.elaborate(Backend.scala:674)
at Chisel.VerilogBackend.elaborate(Verilog.scala:1128)
at Chisel.Driver$.execute(Driver.scala:67)
at Chisel.Driver$.apply(Driver.scala:39)
at Chisel.Driver$.apply(Driver.scala:44)
at Chisel.chiselMain$.apply(hcl.scala:113)
at TestMain$.main(main.scala:8)
at TestMain.main(main.scala)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:57)
at      sun.ref lect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:606)
[trace] Stack trace suppressed: run last compile:run for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last compile:run for the full output.
[error] (compile:run) Nonzero exit code: 1
 [error] Total time: 1 s, completed 21-mag-2014 14.37.31

我的main.scala是：

import Chisel._
import scala.collection.mutable.ArrayBuffer

object TestMain 
{
def main(args: Array[String]): Unit = 
{
    chiselMain(args, () => Module(new DFF()))   
}
}