multithreading - UVM中的多线程

Question

我们如何在 UVM 中加入多线程。UVM testbench中的线程，扩展的UVM组件，序列以及fork和join之间的方法？到目前为止，我已经搜索过这样的多线程测试平台几乎不会对加快仿真时间或提高性能产生影响，除非设计被划分为硬件的多个内核。是这样吗？

Answer 1

To me, both the question and answer show confusion. Ahlawat seems to be asking two questions:

(1) isn't a UVM testbench multi-threaded by its nature? and

(2) if not, can multi-threading be introduced into a UVM testbench?

I think the answer given to question #1 confuses matters, because I think the statement that HDL simulation is multi-threaded by nature is incorrect. HDL simulation tries to model the parallelism in a hardware design, where all the different electronic components are operating in parallel; but, it does not use multi-threading to model this. Instead, HDL simulators (which are, of course, themselves programs) are, at least traditionally, single-threaded programs. It is quite possible to model the effects of parallelism in a single threaded program, and that is what HDL simulators do. Modeling parallelism--which means giving the illusion of things happening at the same time---is not the same as things actually happening at the same time.

Multi-threading means breaking a given program up into multiple programs that are enabled to run simultaneously. Now, it is up to the operating system whether they actually do run simultaneously.

And, the operating system is, in turn, constrained by the processor and memory architecture of the machine.

1. On a multi-core computer, quite likely different threads will run on a single core.
2. On a single-core computer, where the core is of the old fashioned type without the ability to host, inside itself, multiple threads, multi-threading will not, in fact, occur, rather, the different threads will be switched in and out as context switches.

Well, now that all that is said, one aspect of the answer given was on the mark, which is that the fork-join constructs, which are not part of UVM per se, rather of Verilog and System Verilog, allow one to, essentially, tell the operating system that you want certain code in your testbench to run in separate threads. But, this is not a property of the UVM library, per se, it is a Verilog / System Verilog construct.

Answer 2

SystemVerilog/UVM 上下文中的多线程与多核硬件无关。虽然 EDA 供应商确实提供了多核支持，但您无法通过编码来控制它。

也看看这个问题：在多个核心上运行 UVM 阶段。

附带说明：

HDL 仿真本质上是多线程的，因为您必须捕获并行发生的信号更新。SystemVerilog 还允许用户使用构造系列生成自己的并行执行线程fork...join。UVM 本身大量使用此功能来启动例如序列和所有组件的并行运行阶段。如果需要，您当然也可以fork...join在自己的代码中使用来启动自己的并行线程。

另一个注意事项：我认为在 SV 中启动这样的线程的术语是“启动并行进程”。