我正在尝试编写一个断言,该断言仅在信号在“clk”的上升沿转换时才会触发。我写了下面的代码来测试我的想法
module test();
bit clk, clkb;
int d;
assign clkb = ~clk;
initial begin
clk = 0;
forever #100 clk = ~clk;
end
initial begin
d = 10;
#150 d = 20;
end
sva_d_chgd: assert property (@(posedge clk) $stable(d,@(clkb)))
else $error($psprintf("err: time = %0d, clk = %b, d = %0d", $time, clk, d));
always @ (d or clk) begin
$display("time = %0d, clk = %b, d = %0d", $time, clk, d);
if ($time > 200) $finish;
end
endmodule
上面的代码在 VCS 中返回以下输出:
time = 0, clk = 0, d = 10
time = 100, clk = 1, d = 10
"test.vs", 18: test.sva_d_chgd: started at 100s failed at 100s
Offending '$stable(d, @(clkb))'
Error: "test.vs", 18: test.sva_d_chgd: at time 100
err: time = 100, clk = 1, d = 10
time = 150, clk = 1, d = 20
time = 200, clk = 0, d = 20
time = 300, clk = 1, d = 20
$finish called from file "test.vs", line 23.
$finish at simulation time 300
为什么断言在时间 100 时触发,而“d”在时间 150 之前保持稳定?