verilog - Verilog DFF Simulation Producing x for Output

Question

This should be the simplest issue to sort out but for some reason I just can't figure it out. I'm currently teaching myself Verilog and as an exercise have been developing very basic modules and test benches for these modules. One of these modules is the D Flip Flop (DFF). Here is the DFF module (no reset):

module DFF( clk, D, Q );
    parameter n = 1;    // DFF width
    input clk;
    input [n-1:0]  D;
    output [n-1:0] Q;
    reg [n-1:0] Q;

    always @( posedge clk ) begin
        Q <= D;
    end
endmodule

And here is the test bench:

module DFF_tb;
    reg clk, D;
    reg Q;

    DFF #(1) DUT ( clk, D, Q );

    initial begin
        clk = 1'b0;
        forever #10 clk = ~clk;     // Generate clock
    end

    initial begin   
        D = 0;                          // Check D = 0
        if ( Q !== 0 ) $display( "[FAIL] Q = 0" );

        #40 D = 1;                      // Check D = 1
        #40
        if ( Q !== 1 ) $display( "[FAIL] Q = 1" );

        $finish;                            // Complete test
    end
endmodule

And here is the simulation:

The test bench reg Q stays x for the duration of the simulation (thought Q[0] doesn't...).

Any idea why? Thanks!

Answer 1

您不会重置您的触发器，因此在第一个时钟沿之前，Q 没有任何已知值。

通常一个触发器有一个异步复位，它应该在你的测试台上的模拟开始时被断言。FF 中的 always 块应该是：

always @( posedge clk or posedge reset ) begin
  if (reset)
     Q <= '0;
  else
     Q <= D;
end

此外，您不需要将 Q 定义为 reg。它可以是一根电线。edaplayground.com上的工作代码