SystemVerilog 中的循环语句中是否允许并发断言?
module cover12(input clk, in1,in2, in3);
bit mybit;
property prop;
@(posedge clk) in1 ##1 in2 ##1 in3;
endproperty
always @(posedge clk)
begin
for(reg i =0;i<1;i=i+1)
if(mybit)
begin
assert1: assume property(prop);
end
end
endmodule