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任何人将如何在 STD_LOGIC_VECor 上的 VHDL 中执行右移或左移...

它不起作用，为什么？？

AN <= "0001";        
CounterProcess: process(CLK,Switch)
    begin
    if rising_edge(CLK) then
        if prescaler < limit then 
            prescaler <= prescaler + 1;
            else
                prescaler <= (others => '0'); 
                counter <= counter + 1;
                AN sll 1;
        end if;
    end if; 
    end process;
    An <= anode;

    Segment <= counter; 

    end Behavioral;

我收到错误消息：sll 在这种情况下不能有这样的操作数。但是在什么情况下可以使用它，以及如何执行我的左移？

这些是我的包括：

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

不包括执行我的左移操作所需的那个吗？

完整代码

entity Main is
PORT(
        CLK: in std_logic;
        LED: out std_logic_vector (7 downto 0);
        Switch: in std_logic_vector(7 downto 0);
        Segment: out std_logic_vector (7 downto 0); 
        AN: out std_logic_vector (3 downto 0) 
        );

end Main;


architecture Behavioral of Main is
signal counter: std_logic_vector (7 downto 0);
signal prescaler:  std_logic_vector(25 downto 0);
signal limit: std_logic_vector (25 downto 0);
signal anode: std_logic_vector (3 downto 0);
begin
AN <= "0001";

ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz; 
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <=      "00000000000000000000000001"; -- 50 MHz
end case;
end process;


CounterProcess: process(CLK,Switch)
begin
if rising_edge(CLK) then
    if prescaler < limit then 
        prescaler <= prescaler + 1;
        else
            prescaler <= (others => '0'); 
            counter <= counter + 1;
            AN sll AN 1;
    end if;
end if; 
end process;

Segment <= counter; 

end Behavioral;
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2 回答 2

1

除了 trumpetlicks 所说的，请改用这些软件包。确保启用 VHDL-2008 开关。也请先与您的 FPGA 供应商一起尝试，因为这些需要 VHDL-2008 更新：

library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use ieee.numeric_std.all;
   use ieee.numeric_std_unsigned.all;

以上封装均为 IEEE 标准。封装STD_LOGIC_ARITH和std_logic_unsigned不是 IEEE 标准。还要注意numeric_std和STD_LOGIC_ARITH相互冲突，使得很难（超出基本用法）使用类型signed和unsigned。请注意，std_logic_unsigned与numeric_std_unsigned. 因此，如果您的综合工具支持numeric_std_unsigned，我建议您改用它。此外，如果没有，您应该针对它提交错误报告。

于 2014-03-07T00:18:44.743 回答
0

编辑1：

您的代码使用重置逻辑编辑，注意将RESET信号添加到端口列表，删除设置该值的异步行，添加到进程RESET的敏感度列表，添加行，并将您的更改为，以及换档线的变化：CounterProcessif(RESET = '1')ifelsif

我实际上不知道您的An <= Anode线路在做什么，并且认为这也是错误的。

entity Main is PORT(
    RESET:   in  std_logic;
    CLK:     in  std_logic;
    LED:     out std_logic_vector(7 downto 0);
    Switch:  in  std_logic_vector(7 downto 0);
    Segment: out std_logic_vector(7 downto 0); 
    AN:      out std_logic_vector(3 downto 0)
);
end Main;

architecture Behavioral of Main is
signal counter:   std_logic_vector(7  downto 0);
signal prescaler: std_logic_vector(25 downto 0);
signal limit:     std_logic_vector(25 downto 0);
signal anode:     std_logic_vector(3  downto 0);

begin

ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz; 
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <=     "00000000000000000000000001"; -- 50 MHz
end case;
end process;


CounterProcess: process(RESET, CLK, Switch)
begin
    if(RESET = '1') then
        AN <= "0001";
    elsif rising_edge(CLK) then
        if prescaler < limit then 
            prescaler <= prescaler + 1;
        else
            prescaler <= (others => '0'); 
            counter <= counter + 1;
            AN <= std_logic_vector(unsigned(AN) sll 1);
        end if;
    end if;
end process;

An <= anode;
Segment <= counter; 

end Behavioral;

您需要编写当前拥有的行：

AN sll 1;

作为

AN <= AN sll 1;

请记住，这AN本质上就像一个需要“设置”的变量。就像你上面的行

counter <= counter + 1;
于 2014-03-06T12:12:09.973 回答