描述：
我正在尝试为检测 110 或 (2) 1 和 (1) 0 的任何组合的 5 状态顺序状态机生成测试台。我已经编写了代码。见下文。我在测试台上遇到问题，这是错误的。我想测试所有可能的序列以及非序列的输入组合。
请给我一个好的测试台的例子，以实现我需要一台粉状机器。
vhdl 代码：
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity state is
port( clk, x : in std_logic;
z : out std_logic
);
end entity;
architecture behavioral of state is
type state_type is (s0,s1,s2,s3,s4);
signal state,next_s: state_type;
------------------------------------------------------------------------------
begin
process (state,x)
begin
if clk='1' and clk'event then
case state is
when s0 =>
if(x ='0') then
z <= '0';
next_s <= s4;
else
z <= '0';
next_s <= s1;
end if;
when s1 => --when current state is "s1"
if(x ='0') then
z <= '0';
next_s <= s3;
else
z <= '0';
next_s <= s2;
end if;
when s2 => --when current state is "s2"
if(x ='0') then
z <= '1';
next_s <= s0;
else
z <= '0';
next_s <= s0;
end if;
when s3 => --when current state is "s3"
if(x ='0') then
z <= '0';
next_s <= s0;
else
z <= '1';
next_s <= s0;
end if;
when s4 => --when current state is s4
if (x = '0') then
z <= '0';
next_s <= s0;
else
z <= '0';
next_s <= s3;
end if;
end case;
end if;
end process;
end behavioral;
测试台代码：
library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity state_tb is
end state_tb;
architecture TB_ARCHITECTURE of state_tb is
-- Component declaration of the tested unit
component state
port(
clk : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : STD_LOGIC;
signal x : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal z : STD_LOGIC;
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : state
port map (
clk => clk,
x => x,
z => z
);
-- CLOCK STIMULI
CLOCK: process
begin
CLK <= not clk after 20 ns;
wait for 40 ns;
end process;
-- X input STIMULI
X_Stimuli: process
begin
X <= not x after 40 ns;
wait for 80 ns;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_state of state_tb is
for TB_ARCHITECTURE
for UUT : state
use entity work.state(behavioral);
end for;
end for;
end TESTBENCH_FOR_state;